Datasheet
THS8135
SLAS343B –MAY 2001–REVISED APRIL 2013
www.ti.com
Electrical Characteristics
over recommended operating conditions with f
CLK
= 240 MSPS and use of internal reference voltage V
REF
, with
R
FS
= R
FS(nom)
and 37.5-Ω load termination (unless otherwise noted)
Power Supply
1 MHz, -1 dBFS digital sine simultaneously applied to all three channels
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
RGB 89 95 100
AV
DD
= 3.3 V, DV
DD
= 1.8 V,
IAV
DD
Operating supply current, analog YCbCr 71 76 80 mA
CLK = 80 MSPS
Generic (700 mV) 63 66 69
RGB 14.5 15.1 15.7
AV
DD
= 3.3 V, DV
DD
= 1.8 V,
IDV
DD
Operating supply current, digital YCbCr 11.7 12.15 12.7 mA
CLK = 80 MSPS
Generic (700 mV) 14.64 15.1 15.7
RGB 328 338 350
AV
DD
= 3.3 V, DV
DD
= 1.8 V,
P
D
Power dissipation YCbCr 262 270 280 mW
CLK = 80 MSPS
Generic (700 mV) 237 245 252
RGB 89 95 100
AV
DD
= 3.3 V, DV
DD
= 1.8 V,
IAV
DD
Operating supply current, analog mA
CLK = 240 MSPS
Generic (700 mV) 63 66 69
RGB 38 40 41
AV
DD
= 3.3 V, DV
DD
= 1.8 V,
IDV
DD
Operating supply current, digital mA
CLK = 240 MSPS
Generic (700 mV) 38 40 41.1
RGB 373 384 394
AV
DD
= 3.3 V, DV
DD
= 1.8 V,
P
D
Power dissipation mW
CLK = 240 MSPS
Generic (700 mV) 281 290 298
AV
DD
= 3.3 V, DV
DD
= 1.8 V,
IAV
DD
Operating supply current, analog Generic (1.3 V) 114 mA
CLK = 80 MSPS
AV
DD
= 3.3 V, DV
DD
= 1.8 V,
IDV
DD
Operating supply current, digital Generic (1.3 V) 16 mA
CLK = 80 MSPS
AV
DD
= 3.3 V, DV
DD
= 1.8 V,
P
D
Power dissipation Generic (1.3 V) 405 mW
CLK = 80 MSPS
AV
DD
= 3.3 V, DV
DD
= 1.8 V,
IAV
DD
Operating supply current, analog Generic (1.3 V) 114 mA
CLK = 240 MSPS
AV
DD
= 3.3 V, DV
DD
= 1.8 V,
IDV
DD
Operating supply current, digital Generic (1.3 V) 41 mA
CLK = 240 MSPS
AV
DD
= 3.3 V, DV
DD
= 1.8 V,
P
D
Power dissipation Generic (1.3 V) 450 mW
CLK = 240 MSPS
Digital Inputs – DC Characteristics
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
I
IH
High-level input current 1 µA
AV
DD
= 3.3 V, DV
DD
= 1.8 V,
I
IL
Low-level input current -1 µA
Digital inputs and CLK at 0 V for I
IL
,
I
IL(CLK)
Low-level input current, CLK -1 1 µA
Digital inputs and CLK at 2 V for I
IH
I
IH(CLK)
High-level input current, CLK -1 1 µA
C
I
Input capacitance T
A
= 25°C 5 pF
t
s
Data and control inputs setup time 2 ns
t
h
Data and control inputs hold time 500 ps
RGB and YCbCr 4:4:4 7.5
Digital process delay from first registered color CLK
t
d(D)
YCbCr 4:2:2, 2 x 10 bit 9.5
component of pixel
(1)
periods
YCbCr 4:2:2, 1 x 10 bit 10.5
(1) This parameter is assured by design. The digital process delay is defined as the number of CLK cycles required for the first registered
color component of a pixel, starting from the time of registering it on the input bus, to propagate through all processing and appear at the
DAC output drivers. The remaining delay through the IC is the analog delay t
d(A)
of the analog output drivers.
16 Submit Documentation Feedback Copyright © 2001–2013, Texas Instruments Incorporated
Product Folder Links: THS8135