Datasheet

CLK

SYNC

(= SYNC

_delayed)

INS3_INT

M2_INT

(= Not SYNC

_delayed)]

INS3_INT

M2_INT

if (M2 = SYNC_delayed) → M2_INT = L and INS3_INT = H

if (M2 = NOT SYNC

_delayed) → M2_INT = H and INS3_INT = L

THS8135

SLAS343B –MAY 2001–REVISED APRIL 2013

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DAC Outputs

The position of the blanking levels in the THS8135 differs from the position of the blanking levels in the

THS8133. This is to accommodate both full- and reduced-scale configurations on this device, while the THS8133

only supported full-scale. When the DAC output is ac-coupled, as is typically the case, there is no change to the

output video waveform. Typically a clamp circuit at the receiving side will restore the signal to the proper dc level.

Video DAC Mode vs Generic DAC Mode

The THS8133 does not offer a generic DAC mode. The THS8135 uses only the same number of control signals

than the THS8133 but additionally introduces a generic video mode by specific use of a don’t care signal

combination of these control signals on the THS8133.

Programming Example for M2

(1)

Configuration of the device is normally static in a given application, although it is theoretically possible to

reconfigure the device during operation.

If M2_INT and INS3_INT need to be either low or high, the M2 pin is simply tied low or high. If M2_INT and

INS3_INT need to have different levels, these can be easily derived from the signal on the SYNC pin, as shown

in Table 10 and Figure 6.

(1) Programming M1 is analogous.

Table 10. Generating M2 From SYNC

TO HAVE:

APPLY TO M2:

M2_INT INS3_INT

L H ... SYNC delayed by two CLK periods

H L ... inverted SYNC delayed by two CLK periods

M1 can be generated similarly. Therefore, at most one inverter and two flip flops are needed to configure any of

the THS8135 modes using M1 and M2.

Figure 6. Generating INS3_INT and M2_INT From M2

Product Folder Links: THS8135