Datasheet

0 60
Frequency - MHz
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
dBFS
25
30 35
5 15 20 5540 45 5010 65
THS770012
www.ti.com SLOS669C –FEBRUARY 2010–REVISED JANUARY 2012
APPLICATION INFORMATION
THS770012 DRIVING 16-BIT ADC
To illustrate the performance of the THS770012 as an ADC driver, the device is tested with a 16-bit ADC.
For testing purposes, a 30MHz, second-order Butterworth bandpass filter with center frequency at 100MHz is
designed. The design target for the source impedance is 40Ω differential, and for load impedance is 400Ω
differential. Therefore, approximately 1dB insertion loss is expected in the pass-band, requiring the amplifier
output amplitude to be 2.5V
PP
to drive the ADC to –1dBFS.
The output noise voltage specification for the THS770012 is 6 nV/√Hz. With 2.5V
PP
amplifier output voltage
swing and 30MHz bandwidth, the expected SNR from the amplifier + antialias filter is 88.5dBc. When added in
combination with the 16-bit ADC, the expected total SNR is 75.2dBFS for the typical case.
Figure 42 shows the resulting FFT plot when driving the ADC to –1dBFS with a single-tone 95MHz sine wave,
and sampling at 130MSPS. Test results show 100dBc SFDR from the forth-order harmonic and 74.4 dBFS SNR;
analysis of the plot is shown in Table 4 versus typical ADC specifications. The test results from circuit board to
circuit board shows over 10dB of variation in the second order harmonic due to component tolerance. Using
lower 1% tolerance components or adding a balun between the filter and ADC inputs resulted in less variation
and the typical expected results should be better than 95dBc SFDR and 74dB SNR.
Figure 42. FFT Plot of THS770012 + 30MHz BPF + 16-Bit ADC with 95MHz Single-Tone Input Sampling at
130MSPS
Table 4. Analysis of FFT for THS770012 + BPF + 16-Bit ADC at 95MHz vs Typical ADC Specifications
CONFIGURATION ADC INPUT SNR HD2 HD3
THS770012 + BPF + 16Bit ADC –1dBFS 74.4dBFS –101dBc –101dBc
16-Bit ADC Only (typ) –1dBFS 75.2dBFS –100dBc –100dBc
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