Datasheet

THS7375
SBOS449A –SEPTEMBER 2008–REVISED JANUARY 2011 www.ti.com
The DAC must have a defined termination resistance • Ratio = V
INPUT
/V
DAC
to properly set the output voltage. R1 and R2 sum
• R2 = R
TERM
× Ratio
together to accomplish this requirement such that R1
• R1 = R
TERM
– R2
+ R2 = DAC termination resistance.
As an example, the DAC outputs 0.615 V
PP
and
The voltage divider, formed by R1 and R2, also
requires an amplifier gain of 4 V/V (12dB) to achieve
creates a voltage divider that reduces the signal
100% saturated color CVBS signal requirements.
voltage appearing at the THS7375 input terminal. The
Additionally, the DAC requires a termination
voltage appearing at the THS7375 input is equal to
resistance of 75 Ω. Plugging these requirements into
V
DAC
R2/(R1 + R2).
the above equations result in standard resistor values
of R2 = 53.6 Ω and R1 = 21.5 Ω.
Solving for both of these requirements and simplifying
results leads to the general equations:
• DAC termination = R
TERM
= R1 + R2
• V
INPUT
= V
DAC
R2/(R1 + R2)
EVALUATION MODULE
easily done by simply adding a resistor to any of the
To evaluate the THS7375, a product evaluation
following resistor pads; RX1, RX3, RX5, or RX7. A
module (EVM) is available. The EVM allows for
common value to use is 10.8 MΩ. Note that even
testing the THS7375 in many different cnfiguration.
signals with embedded sync can also use bias mode
Inputs and outputs include BNC connectors
if desired.
commonly found in video systems along with 75-Ω
input termination resistors, 75-Ω series source The EVM default output configuration sets all
termination resistors, and 75-Ω characteristic channels for ac output coupling. The 470-mF and
impedance traces. Several unpopulated component 0.1-mF capacitors work well for most ac-coupled
pads are found on the EVM to allow for different input systems. However, if dc-coupled output is desired,
and output configurations as dictated by the user. then replacing the 0.1-mF capacitors—C12, C14, C16,
This EVM is designed to be used with a single-supply and C17—with 0-Ω resistors works well. Removing
from 2.85 V up to 5 V. the 470-mF capacitors is optional, but removing them
from the EVM eliminates a few picofarads of stray
The EVM default input configuration sets all channels
capacitance on each signal path which may be
for dc input coupling. The input signal must be within
desirable.
0 V to about 0.52 V for proper operation with 3.3 V
supply and up to 0.8 V for 5V supply. Failure to be The THS7375EVM incorporates an easy method to
within this range saturates and/or clips the output configure the bypass mode and the disable mode.
signal. If the input range is beyond this range, or if The use of JP1 controls the disable feature while JP4
the signal voltage is unknown, or coming from a controls the bypass feature. While there is a space on
current sink DAC, then ac input configuration is the EVM board for JP2 and JP3, these are not
desireable. This option is easily accomplished with utilized for the THS7375. Connection of JP1 to GND
the EVM by simply replacing Z1, Z2, Z3, and Z4 0-Ω applies 0 V to the disable pin and the THS7375
resistors with 0.1-mF capacitors. operates normally. Moving JP1 to +V
S
causes the
THS7375 to be in disable mode. Connection of JP4
For ac-coupled input and sync-tip clamp (STC)
to GND places the THS7375 in filter mode while
functionality commonly used for CVBS, s-video Y',
moving JP4 to +V
S
places the THS7375 in bypass
component Y' signals, and R'G'B' signals with
mode.
embedded sync, then no other changes are needed.
However, if a bias voltage is needed after the input Figure 55 shows the THS7375EVM schematic.
capacitor which is commonly needed for s-video C', Figure 56 and Figure 57 illustrate the two layers of
component P
'B
and P'
R
, and non-sync embedded the EVM PCB, incorporating standard high-speed
R'G'B' signals, then a pull-up resistor should be layout practices. Table 2 lists the bill of materials as
added to the signal on the EVM. This adjustment is supplied from Texas Instruments.
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