Datasheet

75 W
Y'Out2
CVBSOut2
CVBS
+3.3V
R
DAC/Encoder/SOC
Y’
R
P'
B
R
P'
R
R
1
2
3
4
5
6
7
14
13
12
11
10
9
8
CVBSOUT
HDCH1OUT
HD CH2OUT
HD CH3OUT
V
S+
HDBYPASS
NC
CVBSIN
HDCH1IN
HD CH2IN
HD CH3IN
GND
DISABLE
NC
THS7373
ToGPIOController
orGND
75 W
75 W
P’ Out2
B
75 W
75 W
P’ Out2
R
75 W
75 W
75 W
+3Vto+5V
0.1 Fm
(1)
0.1 Fm
(1)
0.1 Fm
(1)
0.1 Fm
(1)
3.65MW
+3.3V
3.65MW
330 Fm
(2)
+
75 W
CVBSOut1
75 W
330 Fm
(2)
+
75 W
Y'Out1
75 W
330 Fm
(2)
+
75 W
P' Out1
B
75 W
330 Fm
(2)
+
75 W
P' Out1
R
75 W
330 Fm
(2)
+
330 Fm
(2)
+
330 Fm
(2)
+
330 Fm
(2)
+
THS7373
SBOS506A –DECEMBER 2009–REVISED AUGUST 2012 www.ti.com
OUTPUT MODE OF OPERATION: DC- The 80-mA output current drive capability of the
COUPLED THS7373 is designed to drive two video lines
simultaneously per channel—essentially, a 75-Ω
The THS7373 incorporates a rail-to-rail output stage
load—while keeping the output dynamic range as
that can be used to drive the line directly without the
wide as possible. Figure 102 shows the THS7373
need for large ac-coupling capacitors. This design
driving two video lines while keeping the output dc-
offers the best line tilt and field tilt (droop)
coupled.
performance because no ac-coupling occurs. Keep in
mind that if the input is ac-coupled, then the resulting
tilt as a result of the input ac-coupling continues to be
seen on the output, regardless of the output coupling.
(1) This example shows an ac-coupled input. DC-coupling is also allowed as long as the DAC output voltage is within the allowable linear
input and output voltage range of the THS7373. To achieve dc-coupling, remove the 0.1-μF input capacitors and the 3.65-MΩ pull-up
resistors.
(2) This example shows ac-coupled outputs. DC-coupled outputs are also allowed by simply removing the series capacitors on each output.
Figure 102. Typical CVBS + Component Video System with AC-Coupled Inputs and Two Outputs Per
Channel
36 Copyright © 2009–2012, Texas Instruments Incorporated