Datasheet
THS7368
SBOS497 –DECEMBER 2009
www.ti.com
ELECTRICAL CHARACTERISTICS: V
S+
= +5 V (continued)
At T
A
= +25°C, R
L
= 150 Ω to GND, Filter mode, and dc-coupled input/output, unless otherwise noted.
THS7368
TEST
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS LEVEL
(1)
DC PERFORMANCE
V
IN
= 0 V, SD channels 200 305 400 mV A
Biased output voltage
V
IN
= 0 V, SF channels 200 300 400 mV A
Input voltage range DC input, limited by output –0.1/2.3 V C
V
IN
= –0.1 V, SD channels 140 200 μA A
Sync-tip clamp charge current
V
IN
= –0.1 V, SF channels 280 400 μA A
Input impedance 800 || 2 kΩ || pF C
OUTPUT CHARACTERISTICS
R
L
= 150 Ω to +2.5 V 4.85 V C
R
L
= 150 Ω to GND 4.4 4.75 V A
High output voltage swing
R
L
= 75 Ω to +2.5V 4.7 V C
R
L
= 75 Ω to GND 4.5 V C
R
L
= 150 Ω to +2.5 V (V
IN
= –0.2 V) 0.06 V C
R
L
= 150 Ω to GND (V
IN
= –0.2 V) 0.05 0.12 V A
Low output voltage swing
R
L
= 75 Ω to +2.5 V (V
IN
= –0.2 V) 0.1 V C
R
L
= 75 Ω to GND (V
IN
= –0.2 V) 0.05 V C
Output current (sourcing) R
L
= 10 Ω to +2.5 V 90 mA C
Output current (sinking) R
L
= 10 Ω to +2.5 V 85 mA C
POWER SUPPLY
Operating voltage 2.6 5 5.5 V B
V
IN
= 0 V, all channels on 19.7 24.5 30.2 mA A
V
IN
= 0 V, SD channels on, SF channels off 6 7.2 9.5 mA A
Total quiescent current, no load
V
IN
= 0 V, SD channels off, SF channels on 13.7 17.3 20.7 mA A
V
IN
= 0 V, all channels off, V
DISABLE
= 3 V 1 10 μA A
Power-supply rejection ratio
At dc 52 dB C
(PSRR)
LOGIC CHARACTERISTICS
(3)
V
IH
Disabled or Bypass engaged 2.1 1.9 V A
V
IL
Enabled or Bypass disengaged 1.2 1 V A
I
IH
Applied voltage = 3.3 V 1 μA C
I
IL
Applied voltage = 0 V 1 μA C
Disable time 100 ns C
Enable time 100 ns C
Bypass/filter switch time 10 ns C
(3) The logic input pins default to a logic '0' condition when left floating.
Table 2. TRUTH TABLE: V
S+
= +5 V
(1)
FILTER 1 FILTER 2 BYPASS SF
(2)
DESCRIPTION
0 0 0 Selects the standard definition filter (9.5 MHz) for the SF channels
0 1 0 Selects the enhanced definition filter (18 MHz) for the SF channels
1 0 0 Selects the high definition filter (36 MHz) for the SF channels
1 1 0 Selects the full/true high-definition filter (72 MHz) for the SF channels
X X 1 Bypasses the filters for the SF channels
(1) The logic input pins default to a logic '0' condition when left floating.
(2) SF indicates selectable filter.
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