Datasheet

THS7365
SBOS467 – MARCH 2009 .................................................................................................................................................................................................. www.ti.com
ELECTRICAL CHARACTERISTICS: V
S+
= +5 V (continued)
At T
A
= +25 ° C, R
L
= 150 Ω to GND, Filter mode, and dc-coupled input/output, unless otherwise noted.
THS7365
TEST
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS LEVEL
(1)
AC PERFORMANCE (HD CHANNELS) (continued)
Return loss f = 30 MHz, Filter mode 39 dB C
f = 1 MHz, HD to SD channels – 74 dB C
Crosstalk f = 1 MHz, SD to HD channels – 78 dB C
f = 1 MHz, HD to HD channels – 70 dB C
DC PERFORMANCE
V
IN
= 0 V, SD channels 200 310 400 mV A
Biased output voltage
V
IN
= 0 V, HD channels 200 305 400 mV A
Input voltage range DC input, limited by output – 0.1/2.3 V C
V
IN
= – 0.1 V, SD channels 140 200 µ A A
Sync-tip clamp charge current
V
IN
= – 0.1 V, HD channels 280 400 µ A A
Input impedance 800 || 2 k Ω || pF C
OUTPUT CHARACTERISTICS
R
L
= 150 Ω to +2.5 V 4.85 V C
R
L
= 150 Ω to GND 4.5 4.75 V A
High output voltage swing
R
L
= 75 Ω to +2.5V 4.7 V C
R
L
= 75 Ω to GND 4.5 V C
R
L
= 150 Ω to +2.5 V (V
IN
= – 0.2 V) 0.05 V C
R
L
= 150 Ω to GND (V
IN
= – 0.2 V) 0.03 0.1 V A
Low output voltage swing
R
L
= 75 Ω to +2.5 V (V
IN
= – 0.2 V) 0.1 V C
R
L
= 75 Ω to GND (V
IN
= – 0.2 V) 0.05 V C
Output current (sourcing) R
L
= 10 Ω to +2.5 V 90 mA C
Output current (sinking) R
L
= 10 Ω to +2.5 V 85 mA C
POWER SUPPLY
Operating voltage 2.6 5 5.5 V B
V
IN
= 0 V, all channels on 18 21.6 28.5 mA A
V
IN
= 0 V, SD channels on, HD channels off 6 7.2 9.5 mA A
Total quiescent current, no load
V
IN
= 0 V, SD channels off, HD channels on 12 14.4 19 mA A
V
IN
= 0 V, all channels off, V
DISABLE
= 3 V 1 10 µ A A
Power-supply rejection ratio
At dc 52 dB C
(PSRR)
LOGIC CHARACTERISTICS
(2)
V
IH
Disabled or Bypass engaged 2.1 2.2 V A
V
IL
Enabled or Bypass disengaged 0.8 0.8 V A
I
IH
0.2 µ A C
I
IL
0.2 µ A C
Disable time 80 ns C
Enable time 100 ns C
Bypass/filter switch time 5 ns C
(2) The logic input pins should not be left floating. They must be connected to logic low (or GND) or logic high (or V
S+
).
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