Datasheet

THS7353
www.ti.com SLOS484B –NOVEMBER 2005–REVISED AUGUST 2012
ELECTRICAL CHARACTERISTICS, V
S+
= 5 V (continued)
R
L
= 150 Ω to GND, Filter Select = 9 MHz, Input Bias = dc, Adjust pin shorted to the output pin (unless otherwise noted).
TYP OVERTEMPERATURE
PARAMETER TEST CONDITIONS
–40°C to
25°C 25°C 0°C to 70°C UNITS MIN/MAX
85°C
Bias = dc + 250 mV, V
I
= 0 V 260 225/305 215/315 205/325 mV Min/Max
Bias output voltage
Bias = ac 1.55 1.4/1.7 1.35/1.75 1.35/1.75 V Min/Max
Sync tip clamp voltage Bias = ac STC, clamp voltage 265 205/325 195/335 190/340 mV Min/Max
Input bias current Bias = dc - implies Ib out of the pin –0.6 –4 –5 –5 μA Max
Average bias current drift Bias = dc 10 nA/°C
Bias = ac STC, low bias 1.7 0.6/3.3 0.5/3.5 0.4/3.6 μA Min/Max
Sync tip clamp bias current Bias = ac STC, mid bias 6.2 4.3/8.2 4.1/8.4 4/8.5 μA Min/Max
Bias = ac STC, high bias 7.9 6.2/10.8 6/11 5.9/11.1 μA Min/Max
INPUT CHARACTERISTICS
Input voltage range Bias = dc - ensured by out swing 0/3.4 0/2.95 0/2.85 0/2.8 V Min/Max
Bias = ac bias mode 21 kΩ
Input resistance
Bias = dc, dc + 250 mV, ac STC 3 MΩ
Input capacitance 2 pF
OUTPUT CHARACTERISTICS
R
L
= 150 Ω to Midrail 3.4 V
High output voltage swing
R
L
= 150 Ω to GND 3.4 2.95 2.85 2.8 V Min
(limited by input voltage with
R
L
= 75 Ω to Midrail 3.4 V
gain = 0 dB)
R
L
= 75 Ω to GND 3.4 V
R
L
= 150 Ω to Midrail 0.2 0.34 0.37 0.37 V Max
R
L
= 150 Ω to GND 0.09 0.23 0.26 0.27 V Max
Low output voltage swing
R
L
= 75 Ω to Midrail 0.35 0.46 0.5 0.5 V Max
R
L
= 75 Ω to GND 0.09 0.23 0.26 0.27 V Max
R
L
= 10 Ω to GND, sourcing 85 60 57 55 mA Min
Output current
R
L
= 10 Ω to Midrail, sinking 85 60 57 55 mA Min
POWER SUPPLY
Maximum operating voltage 5 5.5 5.5 5.5 V Max
Minimum operating voltage 5 2.7 2.7 2.7 V Min
Maximum quiescent current Per channel V
I
= 400 mV 6.5 7.8 8 8.1 mA Max
Minimum quiescent current Per channel V
I
= 400 mV 6.5 5.2 5 4.9 mA Min
Total quiescent current All channels ON, V
I
= 400 mV
(3)
18.75 mA
Power supply rejection
V
S+
= 5.2 V to 4.8 V 45 40 38 37 dB Min
(+PSRR)
DISABLE CHARACTERISTICS
Quiescent current All 3 channels disabled
(4)
0.4 μA
Turn-on time delay (t
ON
) 5 μs
Time reaches 50% of final value after I
2
C
control is completed
Turn-on time delay (t
OFF
) 2 μs
DIGITAL CHARACTERISTICS
(5)
High-level input voltage (V
IH
) 3.5 V Typ
Low-level input voltage (V
IL
) 1.5 V Typ
(3) Due to sharing of internal bias circuitry, the quiescent current, with all channels operating, is less than the single individual channel
quiescent currents added together.
(4) Note that the I
2
C circuitry is still active while in Disable mode. The current shown is while there is no activity with the THS7353 I
2
C
circuitry.
(5) Standard CMOS logic.
Copyright © 2005–2012, Texas Instruments Incorporated 7