Datasheet

THS7353
SLOS484B –NOVEMBER 2005–REVISED AUGUST 2012 www.ti.com
THS7353 Read Phase 2:
Step 7 0
I
2
C Start (Master) S
Step 8 7 6 5 4 3 2 1 0
I
2
C General Address (Master) 0 1 0 1 1 X X 1
Where each X Logic state is defined by I
2
C-A1 and I
2
C-A0 pins being tied to either V
S+
or GND.
Step 9 9
I
2
C Acknowledge (Slave) A
Step 10 7 6 5 4 3 2 1 0
I
2
C Read Data (Slave) Data Data Data Data Data Data Data Data
Where Data is determined by the Logic values contained in the Channel Register.
Step 11 9
I
2
C Not-Acknowledge (Master) A
Step 12 0
I
2
C Stop (Master) P
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