Datasheet

THS7353

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SLOS484B –NOVEMBER 2005–REVISED AUGUST 2012

EXAMPLE—READING FROM THE THS7353

The read operation consists of two phases. The first phase is the address phase. In this phase, an I

C master

initiates a write operation to the THS7353 by generating a start condition (S) followed by the THS7353 I

address, in MSB first bit order, followed by a 0 to indicate a write cycle. After receiving acknowledges from the

THS7353, the master presents the subaddress (channel) of the register it wants to read. After the cycle is

acknowledged (A), the master terminates the cycle immediately by generating a stop condition (P).

The second phase is the data phase. In this phase, an I

C master initiates a read operation to the THS7353 by

generating a start condition followed by the THS7353 I

C address (as shown below for a read operation), in MSB

first bit order, followed by a 1 to indicate a read cycle. After an acknowledge from the THS7353, the I

C master

receives one byte of data from the THS7353. After the data byte has been transferred from the THS7353 to the

master, the master generates a not acknowledge followed by a stop. Similar to the Write function, to read all

channels Steps 1 through 11 must be repeated for each and every channel desired.

THS7353 Read Phase 1:

Step 1 0

C Start (Master) S

Step 2 7 6 5 4 3 2 1 0

C General Address (Master) 0 1 0 1 1 X X 0

Where each X Logic state is defined by I

C-A1 and I

C-A0 pins being tied to either V

S+

or GND.

Step 3 9

C Acknowledge (Slave) A

Step 4 7 6 5 4 3 2 1 0

C Read Channel Address (Master) 0 0 0 0 0 0 Addr Addr

Where Addr is determined by the values shown in Table 2.

Step 5 9

C Acknowledge (Slave) A

Step 6 0

C Start (Master) P