Datasheet

THS7353

SLOS484B –NOVEMBER 2005–REVISED AUGUST 2012

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EXAMPLE—WRITING TO THE THS7353

The proper way to write to the THS7353 is illustrated as follows:

An I

C master initiates a write operation to the THS7353 by generating a start condition (S) followed by the

THS7353 I

C address (as shown below), in MSB first bit order, followed by a 0 to indicate a write cycle. After

receiving an acknowledge from the THS7353, the master presents the subaddress (channel) it wants to write

consisting of one byte of data, MSB first. The THS7353 acknowledges the byte after completion of the

transfer. Finally the master presents the data it wants to write to the register (channel) and the THS7353

acknowledges the byte. The I

C master then terminates the write operation by generating a stop condition

(P). Note that the THS7353 does not support multi-byte transfers. To write to all three channels – or

registers – this procedure must be repeated for each register one series at a time (i.e., repeat steps 1

through 8 for each channel).

Step 1 0

C Start (Master) S

Step 2 7 6 5 4 3 2 1 0

C General Address (Master) 0 1 0 1 1 X X 0

Where each X Logic state is defined by I

C-A1 and I

C-A0 pins being tied to either Vs+ or GND.

Step 3 9

C Acknowledge (Slave) A

Step 4 7 6 5 4 3 2 1 0

C Write Channel Address (Master) 0 0 0 0 0 0 Addr Addr

Where Addr is determined by the values shown in Table 2.

Step 5 9

C Acknowledge (Slave) A

Step 6 7 6 5 4 3 2 1 0

C Write Data (Master) Data Data Data Data Data Data Data Data

Where Data is determined by the values shown in Table 3.

Step 7 9

C Acknowledge (Slave) A

Step 8 0

C Stop (Master) P

For Step 6, an example of the proper bit control for selecting Input B of the MUX, a 720p Y’ channel signal with

AC-STC lowest line tilt and shortest sync filter is 1111 0101.