Datasheet
SCL
SDA
MSB
Slave Address Data
Stop
1 2 3 4 5 6 7 8 99 1 2 3 4 5 6 7 8 9
Acknowledge Acknowledge
Start
Condition
ClockPulsefor
Acknowledgement
Acknowledge
Not Acknowledge
DataOutput
byReceiver
DataOutput
byTransmitter
SCL From
Master
S
1 2
8 9
SCL
SDA
DataLine
Stable;
DataValid
ChangeofData Allowed
THS7353
www.ti.com
SLOS484B –NOVEMBER 2005–REVISED AUGUST 2012
Figure 71. I
2
C Bit Transfer
Figure 72. I
2
C Acknowledge
Figure 73. I
2
C Address and Data Cycles
Copyright © 2005–2012, Texas Instruments Incorporated 35