Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLinear ICsLinear IC - Amplifier - Video buffering Rail-to-rail 150 MHz TSSOP 20

Start

Condition

Stop

Condition

SDA

SCL

THS7353

SLOS484B –NOVEMBER 2005–REVISED AUGUST 2012

www.ti.com

C INTERFACE NOTES

The I

C interface is used to access the internal registers of the THS7353. I

C is a two-wire serial interface

developed by Philips Semiconductor (see the I

C-Bus Specification, Version 2.1, January 2000). The bus

consists of a data line (SDA) and a clock line (SCL) with pull-up structures. When the bus is idle, both SDA and

SCL lines are pulled high. All the I

C compatible devices connect to the I

C bus through open drain I/O pins,

SDA and SCL. A master device, usually a microcontroller or a digital signal processor, controls the bus. The

master is responsible for generating the SCL signal and device addresses. The master also generates specific

conditions that indicate the START and STOP of data transfer. A slave device receives and/or transmits data on

the bus under control of the master device. The THS7353 works as a slave and supports the standard mode

transfer (100 kbps) and fast mode transfer (400 kbps) as defined in the I

C-Bus specification. The THS7353 has

been tested to be fully functional but not ensured with the high-speed mode (3.4 Mbps).

The basic I

C start and stop access cycles are shown in Figure 70.

The basic access cycle consists of the following:

• A start condition

• A slave address cycle

• Any number of data cycles

• A stop condition

Figure 70. I

C Start and Stop Conditions

GENERAL I

C PROTOCOL

• The master initiates data transfer by generating a start condition. The start condition exist when a high-to-low

transition occurs on the SDA line while SCL is high, as shown in Figure 70. All I

C-compatible devices should

recognize a start condition.

• The master then generates the SCL pulses and transmits the 7-bit address and the read/write direction bit

R/W on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition

requires the SDA line to be stable during the entire high period of the clock pulse (see Figure 71). All devices

recognize the address sent by the master and compare it to their internal fixed addresses. Only the slave

device with a matching address generates an acknowledge (see Figure 72) by pulling the SDA line low during

the entire high period of the ninth SCL cycle. On detecting this acknowledge, the master knows that a

communication link with a slave has been established.

• The master generates further SCL cycles to either transmit data to the slave (R/W bit 1) or receive data from

the slave (R/W bit 0). In either case, the receiver needs to acknowledge the data sent by the transmitter. So,

an acknowledge signal can either be generated by the master or by the slave, depending on which one is the

receiver. The 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long

as necessary (See Figure 73).

• To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from low

to high while the SCL line is high (see Figure 70). This releases the bus and stops the communication link

with the addressed slave. All I

C compatible devices must recognize the stop condition. Upon the receipt of a

stop condition, all devices know that the bus is released, and they wait for a start condition followed by a

matching address.