Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLinear ICsLinear IC - Amplifier - Video buffering Rail-to-rail 150 MHz TSSOP 20

In A

ADC/

Video

Decoder

3.3V

LPF

Sync

TIP

Clamp

DC+

250mV

MUTE

Bypass

2:1

1kW

250 W

AC -

BIAS

InB

InputB

Input A

I2C-

SDA

I2C-

SCL

9/16/

35MHz

Out

Gain

Adjust

0.1 Fm

75 W

1of3Channels

THS7353

www.ti.com

SLOS484B –NOVEMBER 2005–REVISED AUGUST 2012

3-Channel Low Power Video Buffer with I

C Control, Selectable Filters, External Gain

Control, 2:1 Input MUX, and Selectable Input Modes

Check for Samples: THS7353

FEATURES

APPLICATIONS

234

• 3-Video Buffers for CVBS, S-Video, SD/ED/HD

• HDTV Video Buffering

Y'P'

, and G'B'R' (R'G'B') Video

• PVR/DVDR Video Buffering

• I

C™ Control of All Functions

• Projector Video Buffering

• Integrated Low-Pass Filters

• USB/Portable Low Power Video Buffering

– 5

Order Butterworth Characteristics

DESCRIPTION

– Selectable Corner Frequencies of 9-MHz,

Fabricated using the new complimentary silicon-

16-MHz, 35-MHz, and Bypass (150-MHz)

germanium (SiGe) BiCom-III process, the THS7353 is

• Selectable Input Bias Modes

a low-power, single-supply 2.7-V to 5-V, 3-channel

– AC-Coupled with Sync-Tip Clamp

integrated video buffer. It incorporates a selectable

order Butterworth anti-aliasing / DAC

– AC-Coupled with Bias

reconstruction filter to eliminate data converter

– DC-Coupled with 250-mV Input Shift

images. The 9-MHz is a perfect choice for SDTV

– DC-Coupled

video including composite, S-Video™, and 480i/576i

• 2:1 Input MUX Allows Multiple Input Sources

Y'P'

or G'B'R' (R'G'B') video. The 16-MHz filter is

ideal for EDTV 480p/576p Y'P'

, G'B'R', and VGA

• External Gain Control Range From

signals. The 35-MHz filter is useful for HDTV

0 dB to 14 dB

720p/1080i Y'P'

, G'B'R', and SVGA/XGA signals.

• 2.7-V to 5-V Single Supply Operation

For 1080p or SXGA/UXGA signals, the filter can be

• Low 16.2-mA (3.3 V) Total Quiescent Current

bypassed allowing a 150-MHz bandwidth, 300-V/μs

amplifier to buffer the signal.

• Disable (< 1 μA) and Mute Control Functions

Each channel of the THS7353 is individually I

• Rail-to-Rail Output:

configurable for all functions which makes it flexible

– Allows AC or DC Output Coupling

for any application. Its rail-to-rail output stage allows

• Low Differential Gain/Phase of 0.15%/0.3°

for both ac and dc coupling applications. The

externally controlled gain adjust pin allows for fine

tuning of the gain such as line driving, compensating

for cable losses, or Sin-X/X compensation.

Figure 1. 3.3 V Single-Supply AC-Input/AC-Video Output System w/SAG Correction

(1 of 3 Channels Shown)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

C is a trademark of NXP Semiconductors.

3S-Video is a trademark of of its respective owner.

4All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (55 pages)

PAGE 1
THS7353 www.ti.
PAGE 2
THS7353 SLOS484B – NOVEMBER 2005 – REVISED AUGUST 2012 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
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THS7353 www.ti.com SLOS484B – NOVEMBER 2005 – REVISED AUGUST 2012 RECOMMENDED OPERATING CONDITIONS MIN NOM MAX UNIT VSS Supply voltage, VS+ 2.7 5 V TA Ambient temperature –40 85 °C ELECTRICAL CHARACTERISTICS, VS+ = 3.3 V RL = 150 Ω to GND, Filter Select = 9 MHz, Input Bias = dc, Gain Adjust pin shorted to the output pin (unless otherwise noted).
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THS7353 SLOS484B – NOVEMBER 2005 – REVISED AUGUST 2012 www.ti.com ELECTRICAL CHARACTERISTICS, VS+ = 3.3 V (continued) RL = 150 Ω to GND, Filter Select = 9 MHz, Input Bias = dc, Gain Adjust pin shorted to the output pin (unless otherwise noted). TYP PARAMETER TEST CONDITIONS 25°C OVERTEMPERATURE 25°C 0°C to 70°C –40°C to 85°C UNITS Filter Select = 9 MHz: at 5.
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THS7353 www.ti.com SLOS484B – NOVEMBER 2005 – REVISED AUGUST 2012 ELECTRICAL CHARACTERISTICS, VS+ = 3.3 V (continued) RL = 150 Ω to GND, Filter Select = 9 MHz, Input Bias = dc, Gain Adjust pin shorted to the output pin (unless otherwise noted). TYP PARAMETER TEST CONDITIONS OVERTEMPERATURE 25°C 25°C 0°C to 70°C –40°C to 85°C UNITS MIN/MAX Maximum operating voltage 3.3 5.5 5.5 5.5 V Max Minimum operating voltage 3.3 2.7 2.7 2.7 V Min 5.9 7.1 7.3 7.4 mA Max 4.7 4.5 4.
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THS7353 SLOS484B – NOVEMBER 2005 – REVISED AUGUST 2012 www.ti.com ELECTRICAL CHARACTERISTICS, VS+ = 5 V RL = 150 Ω to GND, Filter Select = 9 MHz, Input Bias = dc, Adjust pin shorted to the output pin (unless otherwise noted). TYP PARAMETER TEST CONDITIONS 25°C OVERTEMPERATURE 25°C 0°C to 70°C –40°C to 85°C UNITS MIN/MAX AC PERFORMANCE Small-signal bandwidth (–3 dB) VO – 0.
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THS7353 www.ti.com SLOS484B – NOVEMBER 2005 – REVISED AUGUST 2012 ELECTRICAL CHARACTERISTICS, VS+ = 5 V (continued) RL = 150 Ω to GND, Filter Select = 9 MHz, Input Bias = dc, Adjust pin shorted to the output pin (unless otherwise noted). TYP PARAMETER TEST CONDITIONS OVERTEMPERATURE 25°C 25°C Bias = dc + 250 mV, VI = 0 V 260 225/305 Bias = ac 1.55 1.4/1.7 Sync tip clamp voltage Bias = ac STC, clamp voltage 265 205/325 Input bias current Bias = dc - implies Ib out of the pin –0.
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THS7353 SLOS484B – NOVEMBER 2005 – REVISED AUGUST 2012 www.ti.com TIMING REQUIREMENTS (1) VS+ = 2.7 V to 5 V STANDARD MODE PARAMETER MIN MAX 100 FAST MODE MIN MAX 0 400 UNIT fSCL Clock frequency, SCL 0 tw(H) Pulse duration, SCL high 4 0.6 μs tw(L) Pulse duration, SCL low 4.7 1.
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THS7353 www.ti.
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THS7353 SLOS484B – NOVEMBER 2005 – REVISED AUGUST 2012 www.ti.com PIN CONFIGURATION THS7353PW TSSOP (20-Pin) (Top View) NC CH. 1 - INPUT A CH. 1 - OUTPUT CH. 2 - INPUT A CH. 1 - GAIN ADJ. CH. 3 - INPUT A CH. 2 - OUTPUT CH. 1 - INPUT B CH. 2 - GAIN ADJ. CH. 2 - INPUT B CH. 3 - OUTPUT CH. 3 - INPUT B CH. 3 - GAIN ADJ. I2C-A1 I2C-SCL I2C-A0 I2C-SDA VS+ GND A. NC NC indicates there is no internal connection to these pins. It is recommended, but not required, to connect these pins to GND.
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THS7353 www.ti.com SLOS484B – NOVEMBER 2005 – REVISED AUGUST 2012 TYPICAL CHARACTERISTICS SMALL-SIGNAL FREQUENCY RESPONSE SMALL-SIGNAL FREQUENCY RESPONSE 5 0.5 0 −5 Filter = 35 MHz Filter = 16 MHz -1 -1.5 Filter = 9 MHz -2 -2.5 Filter = 16 MHz −15 −20 Filter = 9 MHz −25 −30 −35 VS = 3.3 V, VO = 200 mVPP, −40 −45 RL = 10 kW || 5 pF -3 0.1 Filter = 35 MHz −10 Signal Gain − dB Signal Gain − dB -0.5 Filter = Bypass 0 Filter = Bypass 1 10 f − Frequency − MHz 100 VS = 3.
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THS7353 SLOS484B – NOVEMBER 2005 – REVISED AUGUST 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) SMALL AND LARGE-SIGNAL FREQUENCY RESPONSE OUTPUT IMPEDANCE vs FREQUENCY 100 0.5 VS = 3.3 V 0 ZO − Output Impedance − W VO = 0.2 VPP Signal Gain − dB -0.5 VO = 1 VPP -1 VO = 0.5 VPP -1.5 -2 VSS ==3.3 3.3V, V, V R kW || 5 pF Filter = Bypass L = 10 RL = 10 kW || 5 pF -2.5 -3 0.1 10 f − Frequency − MHz 1 100 10 1 Filter = 9 MHz 0.1 Filter = Bypass 0.01 0.
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THS7353 www.ti.com SLOS484B – NOVEMBER 2005 – REVISED AUGUST 2012 TYPICAL CHARACTERISTICS (continued) SMALL-SIGNAL FREQUENCY RESPONSE WITH CAPACITIVE LOADING SMALL-SIGNAL FREQUENCY RESPONSE WITH 1 pF CAPACITIVE LOAD 10 5 VS = 3.3 V, Filter = Bypass, RL = 10 kW || CL 8 6 0 CL = 25 pF −10 Signal Gain − dB Signal Gain − dB 4 2 CL = 12 pF 0 CL = 7 pF -2 Filter = 9 MHz −15 −20 Filter = 16 MHz −25 −30 Filter = 35 MHz -4 −35 CL = 1 pF -6 −40 VS = 3.
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THS7353 SLOS484B – NOVEMBER 2005 – REVISED AUGUST 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) 576p G'B'R' 2T PULSE VS = 3.3 V 143 mV/div Filter = 16 MHz 143 mV/div 1080i 2T30 PULSE—INPUT SOURCE R’ P’R P’B B’ Y’ G’ t - Time = 40 ns/div t - Time = 80 ns/div Figure 22. Figure 23. 1080i 2T30 PULSE—OUTPUT 1080i 2T30 PULSE—OUTPUT VS = 3.3 V VS = 3.
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THS7353 www.ti.com SLOS484B – NOVEMBER 2005 – REVISED AUGUST 2012 TYPICAL CHARACTERISTICS (continued) CROSSTALK vs FREQUENCY −30 Filter = Bypass −40 Crosstalk − dB INPUT BIAS CURRENT vs TEMPERATURE 9 VS = 3.3 V and 5 V Worst Case Crosstalk Referred to Input RL = 150 W 8 IIB − Input Bias Current − mA −20 Filter = 35 MHz Filter = 16 MHz −50 Filter = 9 MHz −60 −70 VS = 3.3 V STC − High Bias 7 6 STC − Mid Bias 5 4 3 2 STC − Low Bias −80 1 −90 0.
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THS7353 SLOS484B – NOVEMBER 2005 – REVISED AUGUST 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) PHASE vs FREQUENCY SMALL- AND LARGE-SIGNAL FREQUENCY RESPONSE 45 0.5 Filter = 35 MHz Filter = Bypass 0 0 −45 Filter = 35 MHz -0.5 Signal Gain − dB −90 Phase − o Filter = 9 MHz −135 Filter = 16 MHz −180 −225 Filter = 9 MHz -1 Filter = 16 MHz -1.5 VS = 5 V, RL = 10 kW || 5 pF -2 −270 VS = 5 V, VO = 200 mVPP, RL = 10 kW || 5 pF −315 −360 0.1 Solid Line = 200 mVPP, Dashed Line = 2 VPP -2.
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THS7353 www.ti.com SLOS484B – NOVEMBER 2005 – REVISED AUGUST 2012 TYPICAL CHARACTERISTICS (continued) HD2 vs FREQUENCY HD3 vs FREQUENCY −35 VS = 5 V, VO = 2 VPP, −35 VS = 5 V, VO = 2 VPP, RL = 150 W || 5 pF Filter = Bypass 3rd Order Harmonic Distortion − dB 2nd Order Harmonic Distortion − dB −30 RL = 150 W || 5 pF −40 Filter = 35 MHz −45 −50 Filter = 9 MHz −55 −60 Filter = 16 MHz −65 −70 0.1 1 10 Filter = 35 MHz −45 Filter = 16 MHz −50 −65 −75 0.
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THS7353 SLOS484B – NOVEMBER 2005 – REVISED AUGUST 2012 www.ti.
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THS7353 www.ti.com SLOS484B – NOVEMBER 2005 – REVISED AUGUST 2012 TYPICAL CHARACTERISTICS (continued) 1080i 2T30 PULSE VS = 5 V P’R P’R P’B P’B Y’ Y’ t - Time = 40 ns/div t - Time = 40 ns/div Figure 52. Figure 53.
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THS7353 SLOS484B – NOVEMBER 2005 – REVISED AUGUST 2012 www.ti.com APPLICATION INFORMATION The THS7353 is targeted for video output buffer applications. Although it can be used for numerous other applications, the needs and requirements of the video signal are the most important design parameters of the THS7353. Built on the complimentary silicon germanium (SiGe) BiCom-3 process, the THS7353 incorporates many features not typically found in integrated video parts while consuming low power.
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THS7353 www.ti.com SLOS484B – NOVEMBER 2005 – REVISED AUGUST 2012 INPUT OVERVOLTAGE PROTECTION The THS7353 is built using a high-speed complementary bipolar and CMOS process. The internal junction breakdown voltages are low for these very small geometry devices. These breakdowns are reflected in the Absolute Maximum Ratings table. All input and output device pins are protected with internal ESD protection diodes to the power supplies, as shown in Figure 58.
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THS7353 SLOS484B – NOVEMBER 2005 – REVISED AUGUST 2012 www.ti.com placed first in the system. Since the blue color difference channel (P'B) is next and the red color difference channel (P'R) is last, then it also makes logical sense to place the B' signal on the second channel and the R' signal on the third channel respectfully. Thus hardware compatibility is better achieved when using G'B'R' rather than R'G'B'.
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THS7353 www.ti.com SLOS484B – NOVEMBER 2005 – REVISED AUGUST 2012 The input impedance of the THS7353 in this mode of operation is >1 MΩ. This is due to the input buffer being configured as a unity gain amplifier as shown in Figure 60. VS+ Input Internal Circuitry Input Pin Figure 60. Equivalent DC Input Mode Circuit The input stage of the THS7353 is designed with PNP bipolar transistors. Thus, there is a finite amount of bias current flowing out of the THS7353 input pin.
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THS7353 SLOS484B – NOVEMBER 2005 – REVISED AUGUST 2012 www.ti.com Figure 61 shows the equivalent input circuit while in the dc + 250 mV shift mode of operation. VS+ Internal Circuitry Input Pin Input Level Shifter Figure 61. Equivalent DC + 250 mV Input Mode Circuit INPUT MODES OF OPERATION – AC BIAS Other applications require an ac-coupled input.
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THS7353 www.ti.com SLOS484B – NOVEMBER 2005 – REVISED AUGUST 2012 INPUT MODES OF OPERATION – AC SYNC TIP CLAMP The last input mode of operation is the ac with sync-tip-clamp (STC) which also requires a capacitor in series with the input. Note that while the term sync-tip-clamp is used throughout this document, the THS7353 is better termed as a dc restoration circuit based on the way this function is performed. This circuit is an active clamp circuit and not a passive diode clamp function.
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THS7353 SLOS484B – NOVEMBER 2005 – REVISED AUGUST 2012 www.ti.com When the ac sync-tip-clamp (STC) operation is used, there must also be some finite amount of discharge bias current. As previously described, if the input signal goes below the 250-mV clamp level, the internal loop of the THS7353 sources current to increase the voltage appearing at the input pin.
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THS7353 www.ti.com SLOS484B – NOVEMBER 2005 – REVISED AUGUST 2012 OUTPUT MODES OF OPERATION – DC COUPLED The THS7353 incorporates a rail-to-rail output stage that can be used to drive the line directly without the need for large ac-coupling capacitors. This is shown in Figure 64. This offers the best line tilt and field tilt (or droop) performance since there is no ac coupling occurring.
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THS7353 SLOS484B – NOVEMBER 2005 – REVISED AUGUST 2012 www.ti.com OUTPUT MODES OF OPERATION – AC COUPLED A common method of coupling the video signal to an ADC or video decoder is with the use of a 0.1-μF to 1-μF decoupling capacitor. The low 0.8-Ω at 10-MHz output impedance of the THS7353 allows driving an ADC directly without worrying about possible kick-back current from the ADC. Additionally, the THS7353 can be used to drive a video line which is common when using a large capacitor.
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THS7353 www.ti.com SLOS484B – NOVEMBER 2005 – REVISED AUGUST 2012 Due to the edge rates and frequencies of operation, it is recommended – but not required – to place a 0.1-μF to 0.01-μF capacitor in parallel with the large 220-μF to 1000-μF capacitors. These large value capacitors are most commonly aluminum electrolytic.
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THS7353 SLOS484B – NOVEMBER 2005 – REVISED AUGUST 2012 www.ti.com A benefit of the externally configured gain control is it allows for frequency gain manipulation. There are two main reasons to do this. • The first reason is to account for skin-effect losses in cables. Skin-effect accounts for the high-frequency current flow at the edges of a conductor. This results in an increase of resistance as frequency increases. This high frequency resistance is proportional to the square-root of the frequency.
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THS7353 www.ti.com SLOS484B – NOVEMBER 2005 – REVISED AUGUST 2012 LOW-PASS FILTER AND BYPASS MODES Each channel of the THS7353 incorporates a 5th-Order Low-Pass Filter. These video anti-aliasing / reconstruction filters minimize the images from being passed onto the video decoder / ADC or to the line. Depending on the system design, failure to eliminate these images can cause picture quality problems due to aliasing of the data converter.
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THS7353 SLOS484B – NOVEMBER 2005 – REVISED AUGUST 2012 www.ti.com The I2C interface of the THS7353 allows each channel to be configured totally independent of the other channels. One of the benefits is that a multiple output encoder (or DAC) can be routed through one THS7353 with the proper input configuration and low-pass filter required regardless of the signal.
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THS7353 www.ti.com SLOS484B – NOVEMBER 2005 – REVISED AUGUST 2012 0.1 mF Y’ HDTV 480i 576i 480p 576p P’B 720p 1080i 1080p G’B’R’ P’R 3.3 V THS7353 1 mF AC STC 75 W 2 CH.1 IN A CH.1 OUT 19 3 CH.2 IN A CH1. 18 GAIN ADJ AC BIAS 1 mF AC BIAS 4 CH.3 IN A CH.2 OUT 17 5 CH.1 IN B CH2. 16 GAIN ADJ AC STC 75 W CI Ch. 1 NC 20 1 NC CI Ch. 2 AC STC AC BIAS 0.1 mF CBVS VS+ 75 W 6 CH.2 IN B CH.3 OUT 15 7 CH.3 IN B CH3. 14 GAIN ADJ 8 I 2C-A1 I2C-SCL 13 9 I 2C-A0 I2C-SDA 12 10 GND 0.
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THS7353 SLOS484B – NOVEMBER 2005 – REVISED AUGUST 2012 www.ti.com I2C INTERFACE NOTES The I2C interface is used to access the internal registers of the THS7353. I2C is a two-wire serial interface developed by Philips Semiconductor (see the I2C-Bus Specification, Version 2.1, January 2000). The bus consists of a data line (SDA) and a clock line (SCL) with pull-up structures. When the bus is idle, both SDA and SCL lines are pulled high.
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THS7353 www.ti.com SLOS484B – NOVEMBER 2005 – REVISED AUGUST 2012 SDA SCL Data Line Stable; Data Valid Change of Data Allowed Figure 71. I2C Bit Transfer Data Output by Transmitter Not Acknowledge Data Output by Receiver Acknowledge SCL From Master 1 8 2 9 S Clock Pulse for Acknowledgement Start Condition Figure 72. I2C Acknowledge 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 SCL SDA Stop MSB Acknowledge Slave Address Acknowledge Data Figure 73.
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THS7353 SLOS484B – NOVEMBER 2005 – REVISED AUGUST 2012 www.ti.com During a write cycle, the transmitting device must not drive the SDA signal line during the acknowledge cycle, so that the receiving device may drive the SDA signal low. After each byte transfer following the address byte, the receiving device pulls the SDA line low for one SCL clock cycle. A stop condition is initiated by the transmitting device after the last byte is transferred.
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THS7353 www.ti.com SLOS484B – NOVEMBER 2005 – REVISED AUGUST 2012 I2C DESIGN NOTES: ISSUES AND SOLUTIONS The THS7353 requires some special attention to the I2C function that is usually not required. These are known design issues, but there are simple workarounds that allow the THS7353 to perform within any I2C system. The first known I2C issue is with respect to the power-up condition. On power up, the THS7353 registers are in a random state from device to device.
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THS7353 SLOS484B – NOVEMBER 2005 – REVISED AUGUST 2012 www.ti.com Channel Selection Register Description (Subaddress) The THS7353 operates using only a single byte transfer protocol similar to Figure 74 and Figure 76. The internal subaddress registers and the functionality of each are found in Table 2. When writing to the device, it is required to send one byte of data to the corresponding internal subaddress.
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THS7353 www.ti.com SLOS484B – NOVEMBER 2005 – REVISED AUGUST 2012 Channel Register Bit Descriptions Each bit of the subaddress (channel selection) control register as described above allows the user to individually control the functionality of the THS7353. The benefit of this process allows the user to control the functionality of each channel independent of the other channels. The bit description is decoded in Table 3. Table 3.
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THS7353 SLOS484B – NOVEMBER 2005 – REVISED AUGUST 2012 www.ti.com EXAMPLE—WRITING TO THE THS7353 The proper way to write to the THS7353 is illustrated as follows: An I2C master initiates a write operation to the THS7353 by generating a start condition (S) followed by the THS7353 I2C address (as shown below), in MSB first bit order, followed by a 0 to indicate a write cycle.
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THS7353 www.ti.com SLOS484B – NOVEMBER 2005 – REVISED AUGUST 2012 EXAMPLE—READING FROM THE THS7353 The read operation consists of two phases. The first phase is the address phase. In this phase, an I2C master initiates a write operation to the THS7353 by generating a start condition (S) followed by the THS7353 I2C address, in MSB first bit order, followed by a 0 to indicate a write cycle.
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THS7353 SLOS484B – NOVEMBER 2005 – REVISED AUGUST 2012 www.ti.com THS7353 Read Phase 2: Step 7 0 I2C Start (Master) S Step 8 2 I C General Address (Master) 7 6 5 4 3 2 1 0 0 1 0 1 1 X X 1 Where each X Logic state is defined by I2C-A1 and I2C-A0 pins being tied to either VS+ or GND.
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THS7353 www.ti.com SLOS484B – NOVEMBER 2005 – REVISED AUGUST 2012 Evaluation Module To evaluate the THS7353, an evaluation module (EVM) is available. Because the THS7353 is controlled by the I2C lines, additional control is required rather than simple switches. To keep the control as easy as possible, an USB-to-I2C interface was designed onto the EVM. A computer running either Windows 2000 or XP is then connected to the EVM through the USB cable.
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THS7353 SLOS484B – NOVEMBER 2005 – REVISED AUGUST 2012 www.ti.com Table 4. Bill Of Materials (continued) ITEM 44 DESCRIPTION SMD SIZE REFERENCE DESIGNATOR PCB QUANTITY MANUFACTURER'S PART NUMBER (1) DISTRIBUTOR'S PART NUMBER 19 RESISTOR, 75 OHM, 1/8W, 1% 0805 R5, R8, R10, R11, R12, R14, R17, R18, R22 9 (ROHM) MCR10EZHF75.0 (DIGI-KEY) RHM75.
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THS7353 www.ti.com SLOS484B – NOVEMBER 2005 – REVISED AUGUST 2012 Figure 78.
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THS7353 SLOS484B – NOVEMBER 2005 – REVISED AUGUST 2012 www.ti.com Figure 79.
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THS7353 www.ti.com SLOS484B – NOVEMBER 2005 – REVISED AUGUST 2012 Figure 80.
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THS7353 SLOS484B – NOVEMBER 2005 – REVISED AUGUST 2012 www.ti.com Figure 81.
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THS7353 www.ti.com SLOS484B – NOVEMBER 2005 – REVISED AUGUST 2012 REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (January 2010) to Revision B • Page Added I2C Design Notes: Issues and Solutions section .....................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 17-Aug-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device THS7353PWR Package Package Pins Type Drawing TSSOP PW 20 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2000 330.0 16.4 Pack Materials-Page 1 6.95 B0 (mm) K0 (mm) P1 (mm) 7.1 1.6 8.0 W Pin1 (mm) Quadrant 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 17-Aug-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) THS7353PWR TSSOP PW 20 2000 367.0 367.0 38.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.