Datasheet

t
w(H)
t
w(L)
t
r
t
f
t
su(1)
t
h(1)
SCL
SDA
t
su(2)
t
h(2)
t
su(3)
t
(buf)
SCL
SDA
StartCondition StopCondition
THS7347
www.ti.com SLOS531B –MAY 2007– REVISED OCTOBER 2011
TIMING REQUIREMENTS FOR I
2
C INTERFACE
(1)(2)
At V
DD
= 2.7 V to 5 V.
STANDARD MODE FAST MODE
PARAMETER MIN MAX MIN MAX UNIT
f
SCL
Clock frequency, SCL 0 100 0 400 kHz
t
w(H)
Pulse duration, SCL high 4 0.6 μs
t
w(L)
Pulse duration, SCL low 4.7 1.3 μs
t
r
Rise time, SCL and SDA 1000 300 ns
t
f
Fall time, SCL and SDA 300 300 ns
t
su(1)
Setup time, SDA to SCL 250 100 ns
t
h(1)
Hold time, SCL to SDA 0 0 ns
t
(buf)
Bus free time between stop and start conditions 4.7 1.3 μs
t
su(2)
Setup time, SCL to start condition 4.7 0.6 μs
t
h(2)
Hold time, start condition to SCL 4 0.6 μs
t
su(3)
Setup time, SCL to stop condition 4 0.6 μs
C
b
Capacitive load for each bus line 400 400 pF
(1) The THS7347 I
2
C address = 01011(A1)(A0)(R/W). See the Applications Information section for more information.
(2) The THS7347 was designed to comply with version 2.1 of the I
2
C specification.
Figure 1. SCL and SDA Timing
Figure 2. Start and Stop Conditions
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