Datasheet

THS7347

SLOS531B –MAY 2007– REVISED OCTOBER 2011

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THS7347 Read Phase 2:

Step 7 0

C Start (Master) S

Step 8 7 6 5 4 3 2 1 0

C General Address (Master) 0 1 0 1 1 X X 1

Where each X Logic state is defined by I

C-A1 and I

C-A0 pins being tied to either V

or GND.

Step 9 9

C Acknowledge (Slave) A

Step 10 7 6 5 4 3 2 1 0

C Read Data (Slave) Data Data Data Data Data Data Data Data

Where Data is determined by the logic values contained in the Channel Register.

Step 11 9

C Not-Acknowledge (Master) A

Step 12 0

C Stop (Master) P