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THS7347

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SLOS531B –MAY 2007– REVISED OCTOBER 2011

Slave Address

Both the SDA and the SCL must be connected to a positive supply voltage via a pull-up resistor. These resistors

should range from 2 kΩ to 19 kΩ in order to comply with the I

C specification. When the bus is free, both lines

are high. The address byte is the first byte received following the START condition from the master device. The

first five bits (MSBs) of the address are factory-preset to 01011. The next two bits of the THS7347 address are

controlled by the logic levels appearing on the I

C, A1 and I

C, A0 pins. The I

C, A1 and I

C, A0 address inputs

can be connected to V

for logic 1, GND for logic 0, or actively driven by TTL/CMOS logic levels. The device

address is set by the state of these pins and is not latched. Thus, a dynamic address control system could be

used to incorporate several devices on the same system. Up to four THS7347 devices can be connected to the

same I

C bus without requiring additional glue logic. Table 1 lists the possible addresses for the THS7347.

Table 1. THS7347 Slave Addresses

SELECTABLE WITH READ/WRITE

FIXED ADDRESS ADDRESS PINS BIT

Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 (A1) Bit 1 (A0) Bit 0 (R/W)

0 1 0 1 1 0 0 0

0 1 0 1 1 0 0 1

0 1 0 1 1 0 1 0

0 1 0 1 1 0 1 1

0 1 0 1 1 1 0 0

0 1 0 1 1 1 0 1

0 1 0 1 1 1 1 0

0 1 0 1 1 1 1 1

Channel Selection Register Description (Subaddress) and Power-Up Condition (PUC) Pin

The THS7347 operates using only a single-byte transfer protocol similar to that illustrated in Figure 9 and

Figure 11. The internal subaddress registers and the functionality of each are given in Table 2. When writing to

the device, it is required to send one byte of data to the corresponding internal subaddress. If control of all three

channels is desired, then the master must cycle through all the subaddresses (channels) one at a time; see the

example, Writing to the THS7347 (in WRITE AND READ EXAMPLES) for the proper procedure of writing to the

THS7347.

During a read cycle, the THS7347 sends the data in its selected subaddress (or channel) in a single transfer to

the master device requesting the information. See the Reading from the THS7347 example (in WRITE AND

READ EXAMPLES) for the proper procedure on reading from the THS7347.

On power-up, the THS7347 registers are dictated by the Power-Up Control (PUC) pin. If the PUC pin is tied to

GND, the THS7347 powers up in a fully disabled state. If the PUC pin is tied to V

, upon power-up the

THS7347 is configured in the following state: ADC buffers disabled, monitor pass-through enabled, and ac-bias

on, for all three input channels. It remains in the state dictated by the PUC unti a valid write sequence is

completed.

Table 2. THS7347 Channel Selection Register Bit Assignments

BIT ADDRESS

....b

)

Channel 1 0000 0001

Channel 2 0000 0010

Channel 3 0000 0011

Channel H Sync, Channel V Sync, and

0000 0100

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