Datasheet
EVALUATION MODULE
+
J3
J1
J2
R1
75W
R3
75W
R2
75W
A1
A2
C1
B1
B2
A3
C2
C3
B3
JP1
1
R7
1kW
U1
R4
75W
R6
75W
R5
75W
J4
J6
J5
C3
0.1 Fm
C2
0.1 Fm
C1
100 F,10Vm
FB1
GND
V
S+
J7 J8
THS7319
SBOS468A – JUNE 2009 – REVISED JULY 2009 ..............................................................................................................................................................
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To evaluate the THS7319, an evaluation module The THS7319 incorporates an easy method to
(EVM) is available. The EVM allows dc-coupled input configure the enable mode. JP1 controls the enable
and output configurations. Inputs and outputs include feature. Connecting JP1 to GND applies 0 V to the
BNC connectors commonly found in video systems enable pin and the THS7319 is placed into shutdown
along with 75- Ω input termination resistors, 75- Ω mode consuming nominally 0.15 µ A of quiescent
series source termination resistors, and 75- Ω current. Moving JP1 to +V
S
causes the THS7319 to
characteristic impedance traces. This EVM is be in normal operation mode where the quiescent
designed to be used with a single supply from 2.6 V current should be nominally 3.4 mA for the entire
up to 5 V. EVM. This quiescent current is with no load or no
signal applied on the input. Adding a load and/or
The EVM input configuration sets all channels for dc
input signal causes the quiescent current to vary
input coupling. The input signal must be within 0 V to
accordingly.
approximately 1.5 V for proper operation. Failure to
be within this range saturates and/or clips the output Figure 57 shows the EVM schematic. Figure 58 and
signal. Refer to the Application Information section for Figure 59 illustrate the two layers of the EVM PCB,
further information. incorporating standard high-speed layout practices.
Table 5 lists the bill of materials as the board comes
supplied from Texas Instruments.
Figure 57. THS7319 EVM Schematic
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Product Folder Link(s): THS7319