Datasheet

MinSpace S
T TraceWidth
MetalDiameter
SeeDimension
orA C
X Pitch
Y Pitch
THS7319
SBOS468A – JUNE 2009 – REVISED JULY 2009 .............................................................................................................................................................. www.ti.com
(1) Circuit traces from the NSMD-defined PWB lands should be 75- µ m to 100- µ m wide in the exposed area inside the solder mask opening.
Wider trace widths reduce device stand-off and impact reliability.
(2) Best reliability results are achieved when the PWB laminate glass transition temperature is greater than the operating temperature range
of the intended application.
(3) For a PWB using a Ni/Au surface-finish, the Au thickness should be less than 0.5 µ m to avoid a reduction in thermal fatigue performance.
(4) Solder mask thickness should be less than 20 µ m above the copper circuit pattern.
(5) Best solder stencil performance is achieved using laser-cut stencils with electro-polishing. Use of chemically-etched stencils results in
inferior solder-paste volume control.
(6) Trace routing away from the MicrostarCSP device should be balanced in X and Y directions to avoid unintentional component movement
because of solder wetting forces.
Figure 54. Trace Width/Spacing Example
Table 3. Definitions for Figure 54
( S or T) TRACE
PAD PACKAGE PITCH ( A or C) METAL DIAMETER
WIDTH/SPACING
NSMD 0.50 mm 0.25 mm 0.08 mm
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