Datasheet

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INPUT OVERVOLTAGE PROTECTION
External
Input/
Output
Pin
Internal
Circuitry
V
S+
TYPICAL CONFIGURATION and VIDEO TERMINOLOGY
DaVinci/
DM2xx/
DM3xx/
OMAP
TM
CVBS
Y’
C’
75 W
Y’
OUT
75 W
C’
OUT
75 W
+1.8V
75 W
75 W
SDTV
CVBS
S-Video Y’
S-VideoC’
480i/576i
Y’P’ P’
G’B’R’
B R
75 W
S-Video
500 W
500 W
500 W
5
8
7
6
1
2
3
4
V
S+
GND
CH.2IN
CH.3IN
CH.1IN
CH.3OUT
CH.2OUT
CH.1OUT
THS7315
CVBS
OUT
+
+
+
+3.3V
22 Fm
0.1 Fm
0.1 Fm
330 Fm
330 Fm
Gain=
5.2V/V
THS7315
SLOS532 – JUNE 2007
APPLICATION INFORMATION (continued)
The THS7315 is built using a very high-speed complementary bipolar and CMOS process. The internal junction
breakdown voltages are relatively low for these very small geometry devices. These breakdowns are reflected in
the Absolute Maximum Ratings table. All input and output device pins are protected with internal ESD protection
diodes to the power supplies, as shown in Figure 3 .
Figure 3. Internal ESD Protection
These diodes provide moderate protection to input overdrive voltages above and below the supplies as well. The
protection diodes can typically support 30 mA of continuous current when overdriven.
A typical application circuit using the THS7315 as a video buffer is shown in Figure 4 . It shows a video DAC
output, such as the DaVinci, driving the three input channels of the THS7315. Although the S-Video Y’/C’
channels and the composite video (CVBS) channel of an SD video system are shown, these channels can easily
be the Y’P’
B
P’
R
(sometimes labeled Y’U’V’ or incorrectly labeled Y’C’
B
C’
R
) signals of a 480i or 576i system.
These signals can also be G’B’R’ (R'G'B') signals or other variations. Note that for computer signals, the sync
should be embedded within the signal for a system with only three outputs. This configuration is sometimes
labeled as R’G’sB’ (sync on green) or R’sG’sB’s (sync on all signals).
Figure 4. Typical SDTV CVBS/Y'/C' Inputs From DC-Coupled Encoder/DAC
With AC-Coupled Line Driving
8
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