Datasheet
Table Of Contents
- FEATURES
- APPLICATIONS
- DESCRIPTION
- DESCRIPTION (continued)
- ABSOLUTE MAXIMUM RATINGS
- DISSIPATION RATINGS
- RECOMMENDED OPERATING CONDITIONS
- ELECTRICAL CHARACTERISTICS: VS+ = 3.3 V
- ELECTRICAL CHARACTERISTICS: VS+ = 5 V
- TIMING REQUIREMENTS
- FUNCTIONAL BLOCK DIAGRAM
- PIN CONFIGURATION
- TYPICAL CHARACTERISTICS
- TYPICAL CHARACTERISTICS: VS+ = 3.3 V
- TYPICAL CHARACTERISTICS: VS+ = 5 V
- APPLICATION INFORMATION
- OPERATING VOLTAGE
- INPUT OVERVOLTAGE PROTECTION
- TYPICAL CONFIGURATION and VIDEO TERMINOLOGY
- INPUT MODES OF OPERATION: DC
- INPUT MODES OF OPERATION: DC + 135-mV SHIFT
- INPUT MODES OF OPERATION: AC BIAS
- INPUT MODES OF OPERATION: AC SYNC-TIP-CLAMP
- OUTPUT MODES OF OPERATION: DC COUPLED
- OUTPUT MODES OF OPERATION: AC-COUPLED
- OUTPUT MODES OF OPERATION: AC-COUPLED WITH SAG CORRECTION
- INCREASING GAIN
- LOW-PASS FILTER AND BYPASS MODES
- BENEFITS OF THS7303 OVER PASSIVE FILTERING
- I2C INTERFACE NOTES
- GENERAL I2C PROTOCOL
- I2C DESIGN NOTES: ISSUES AND SOLUTIONS
- SLAVE ADDRESS
- CHANNEL SELECTION REGISTER DESCRIPTION (SUB-ADDRESS)
- CHANNEL REGISTER BIT DESCRIPTIONS
- EXAMPLE: WRITING TO THE THS7303
- EXAMPLE: READING FROM THE THS7303
- EVALUATION MODULE
- EVM BOARD LAYERS
- Revision History
THS7303
www.ti.com
SLOS479B –OCTOBER 2005– REVISED MARCH 2011
EXAMPLE: READING FROM THE THS7303
The read operation consists of two phases. The first phase is the address phase, where an I
2
C master initiates a
write operation to the THS7303 by generating a start condition (S) followed by the THS7303 I
2
C address in MSB
first bit order, followed by a '0' to indicate a write cycle. After receiving acknowledges from the THS7303, the
master presents the sub-address (channel) of the register it wants to read. After the cycle is acknowledged (A),
the master terminates the cycle immediately by generating a stop condition (P).
The second phase is the data phase. In this phase, an I
2
C master initiates a read operation to the THS7303 by
generating a start condition followed by the THS7303 I
2
C address in MSB first bit order, followed by a '1' to
indicate a read cycle. After an acknowledge from the THS7303, the I
2
C master receives one byte of data from
the THS7303. After the data byte has been transferred from the THS7303 to the master, the master generates a
not acknowledge (A) followed by a stop. As with the write function, in order to read all channels, steps 1 through
11 must be repeated for each channel desired.
Example of THS7303 Read Phase 1:
Step 1 0
I
2
C Start (Master) S
Step 2 7 6 5 4 3 2 1 0
I
2
C General Address (Master) 0 1 0 1 1 X X 0
Where each X logic state is defined by I
2
C A1 and I
2
C A0 pins being tied to either V
S+
or GND.
Step 3 9
I
2
C Acknowledge (Slave) A
Step 4 7 6 5 4 3 2 1 0
I
2
C Read Channel Address (Master) 0 0 0 0 0 0 Addr Addr
Where Addr is determined by the values shown in Table 2.
Step 5 9
I
2
C Acknowledge (Slave) A
Step 6 0
I
2
C Start (Master) P
Example of THS7303 Read Phase 2:
Step 7 0
I
2
C Start (Master) S
Step 8 7 6 5 4 3 2 1 0
I
2
C General Address (Master) 0 1 0 1 1 X X 1
Where each X logic state is defined by I
2
C A1 and I
2
C A0 pins being tied to either V
S+
or GND.
Step 9 9
I
2
C Acknowledge (Slave) A
Step 10 7 6 5 4 3 2 1 0
I
2
C Read Data (Slave) Data Data Data Data Data Data Data Data
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