Datasheet

THS7303
www.ti.com SLOS479B –OCTOBER 2005– REVISED MARCH 2011
CHANNEL REGISTER BIT DESCRIPTIONS
Each bit of the sub-address (channel selection) control register as described in Table 2 allows the user to
individually control the functionality of the THS7303. The benefit of this process allows the functionality of each
channel to be controlled independently of the other channels. The bit description is decoded in Table 3.
Table 3. THS7303 Channel Register Bit Decoder Table
BIT
BIT FUNCTION VALUE(S) RESULT
0 0 500-kHz filter—Useful for 9-MHz video LPF
0 1 2.5-MHz filter—Useful for 16-MHz video LPF
(MSB)
STC Low-Pass Filter Selection
7, 6
1 0 5-MHz filter—Useful for 35-MHz/bypass video LPF
1 1 5-MHz filter—Useful for 35-MHz/bypass video LPF
0 Input A select
5 Input MUX Selection
1 Input B select
0 0 9-MHz LPF—Useful for SDTV, S-Video, 480i/576i
0 1 16-MHz LPF—Useful for EDTV 480p/576p and VGA
Low-Pass Filter
4 , 3
Frequency Selection
1 0 35-MHz LPF—Useful for 720p, 1080i, and SVGA/XGA
1 1 Bypass LPF—Useful for 1080p and SXGA/UXGA
0 0 0 Disable channel—Conserves power
0 0 1 Channel on—Mute function—No output
0 1 0 Channel on—DC bias select
0 1 1 Channel on—DC bias + 135 mV offset select
2, 1, 0 Input Bias Mode Selection and
(LSB) Disable Control
1 0 0 Channel on—AC bias select
1 0 1 Channel on—Sync-tip-clamp with low bias
1 1 0 Channel on—Sync-tip-clamp with mid bias
1 1 1 Channel on—Sync-tip-clamp with high bias
Bits 7 (MSB) and 6 – Controls the AC Sync-Tip-Clamp Low-Pass Filter function. If ac STC mode is not used, this
function is ignored.
Bit 5 – Controls the input MUX of the THS7303.
Bits 4 and 3 – Controls the fifth-order low-pass filter –3 dB corner frequency or the bypass mode of operation.
Bits 2, 1, and 0 (LSB) – Selects the input biasing of the THS7303 and the power-savings function. When
sync-tip-clamp is selected, the dc input sink bias current is also selectable.
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