Datasheet
Table Of Contents
- FEATURES
- APPLICATIONS
- DESCRIPTION
- DESCRIPTION (continued)
- ABSOLUTE MAXIMUM RATINGS
- DISSIPATION RATINGS
- RECOMMENDED OPERATING CONDITIONS
- ELECTRICAL CHARACTERISTICS: VS+ = 3.3 V
- ELECTRICAL CHARACTERISTICS: VS+ = 5 V
- TIMING REQUIREMENTS
- FUNCTIONAL BLOCK DIAGRAM
- PIN CONFIGURATION
- TYPICAL CHARACTERISTICS
- TYPICAL CHARACTERISTICS: VS+ = 3.3 V
- TYPICAL CHARACTERISTICS: VS+ = 5 V
- APPLICATION INFORMATION
- OPERATING VOLTAGE
- INPUT OVERVOLTAGE PROTECTION
- TYPICAL CONFIGURATION and VIDEO TERMINOLOGY
- INPUT MODES OF OPERATION: DC
- INPUT MODES OF OPERATION: DC + 135-mV SHIFT
- INPUT MODES OF OPERATION: AC BIAS
- INPUT MODES OF OPERATION: AC SYNC-TIP-CLAMP
- OUTPUT MODES OF OPERATION: DC COUPLED
- OUTPUT MODES OF OPERATION: AC-COUPLED
- OUTPUT MODES OF OPERATION: AC-COUPLED WITH SAG CORRECTION
- INCREASING GAIN
- LOW-PASS FILTER AND BYPASS MODES
- BENEFITS OF THS7303 OVER PASSIVE FILTERING
- I2C INTERFACE NOTES
- GENERAL I2C PROTOCOL
- I2C DESIGN NOTES: ISSUES AND SOLUTIONS
- SLAVE ADDRESS
- CHANNEL SELECTION REGISTER DESCRIPTION (SUB-ADDRESS)
- CHANNEL REGISTER BIT DESCRIPTIONS
- EXAMPLE: WRITING TO THE THS7303
- EXAMPLE: READING FROM THE THS7303
- EVALUATION MODULE
- EVM BOARD LAYERS
- Revision History
THS7303
SLOS479B – OCTOBER 2005– REVISED MARCH 2011
www.ti.com
SLAVE ADDRESS
The slave address byte is the first byte received following the start condition from the master device. The first five
bits (MSBs) of the address are factory preset to '01011'. The next two bits of the THS7303 address are controlled
by the logic levels appearing on the I
2
C A1 and I
2
C A0 pins. The I
2
C A1 and I
2
C A0 address inputs can be
connected to V
S+
for logic 1, GND for logic 0, or can be actively driven by TTL/CMOS logic levels. The device
address is set by the state of these pins and is not latched. Thus, a dynamic address control system can be used
to incorporate several devices on the same system. Up to four THS7303 devices can be connected to the same
I
2
C bus without requiring additional glue logic. Table 1 lists the possible addresses for the THS7303
Table 1. THS7303 Slave Addresses
SELECTABLE WITH READ/WRITE
FIXED ADDRESS ADDRESS PINS BIT
BIt 7 (MSB) BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 (A1) BIT 1 (A0) BIT 0
0 1 0 1 1 0 0 0
0 1 0 1 1 0 0 1
0 1 0 1 1 0 1 0
0 1 0 1 1 0 1 1
0 1 0 1 1 1 0 0
0 1 0 1 1 1 0 1
0 1 0 1 1 1 1 0
0 1 0 1 1 1 1 1
CHANNEL SELECTION REGISTER DESCRIPTION (SUB-ADDRESS)
The THS7303 operates using only a single-byte transfer protocol similar to Figure 75 and Figure 77. The internal
sub-address registers, and the functionality of each, are found in Table 2. When writing to the device, it is
required to send one byte of data to the corresponding internal sub-address. If control of all three channels is
desired, then the master must cycle through all the sub-addresses (channels) one at a time; see the Example:
Writing to the THS7303 section for the proper procedure of writing to the THS7303.
During a read cycle, the THS7303 sends the data in its selected sub-address (or channel) in a single transfer to
the master device requesting the information. See the Example: Reading from the THS7303 section for the
proper procedure on reading from the THS7303.
Table 2. THS7303 Channel Selection Register Bit Assignments
BIT ADDRESS
REGISTER NAME (b7b6b5....b0)
Channel 1 0000 0001
Channel 2 0000 0010
Channel 3 0000 0011
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