Datasheet

A =No Acknowledge(SDA High)
A = Acknowledge
S=StartCondition
P =StopCondition
W=Write
R=Read
A
A A PDATA DATA
S Slave Address
FromTransmitter
FromReceiver
W
A6
A5
2
A0
A1
ACK
Acknowledge
(FromReceiver)
ICDevice Addressand
Read/WriteBit
R/W D7
D6 D0 D0
ACK
Stop
Condition
Acknowledge
(Receiver)
LastDataByte
SDA
D7
D6
D1 D1
FirstData
Byte
Start
Condition
Acknowledge
(Transmitter)
ACK
Other
DataBytes
A =No Acknowledge(SDA High)
A = Acknowledge
S=StartCondition
P =StopCondition
W=Write
R=Read
A
A A PDATA DATA
S Slave Address
Transmitter
Receiver
R
A6
2
A0
ACK
Acknowledge
(From
Receiver)
ICDevice Addressand
Read/WriteBit
R/W D7
D0
ACK
Stop
Condition
Acknowledge
(From
Transmitter)
LastDataByte
SDA
D7
D6
D1
D0
ACK
FirstData
Byte
Start
Condition
Not
Acknowledge
(Transmitter)
Other
DataBytes
THS7303
SLOS479B – OCTOBER 2005– REVISED MARCH 2011 www.ti.com
During a read cycle, the slave receiver acknowledges the initial address byte if it decodes the address as its
address. Following this initial acknowledge by the slave, the master device becomes a receiver and
acknowledges data bytes sent by the slave. When the master has received all of the requested data bytes from
the slave, the not acknowledge (A) condition is initiated by the master by keeping the SDA signal high just before
it asserts the stop condition. This sequence terminates a read cycle, as shown in Figure 77 and Figure 78. Note
that the THS7303 does not allow multiple read transfers to occur. See the Example: Reading from the THS7303
section for the proper procedure on reading from the THS7303.
Figure 75. I
2
C Write Cycle
Figure 76. Multiple Byte Write Transfer
Figure 77. I
2
C Read Cycle
Figure 78. Multiple Byte Read Transfer
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