Datasheet

SCL
SDA
DataLine
Stable;
DataValid
ChangeofData Allowed
Start
Condition
ClockPulsefor
Acknowledgement
Acknowledge
Not Acknowledge
DataOutput
byReceiver
DataOutput
byTransmitter
SCL From
Master
S
1 2
8 9
SCL
SDA
MSB
Slave Address Data
Stop
1 2 3 4 5 6 7 8 99 1 2 3 4 5 6 7 8 9
Acknowledge Acknowledge
THS7303
www.ti.com SLOS479B –OCTOBER 2005– REVISED MARCH 2011
Figure 72. I
2
C Bit Transfer
Figure 73. I
2
C Acknowledge
Figure 74. I
2
C Address and Data Cycles
During a write cycle, the transmitting device must not drive the SDA signal line during the acknowledge cycle, so
that the receiving device may drive the SDA signal low. After each byte transfer following the address byte, the
receiving device pulls the SDA line low for one SCL clock cycle. A stop condition is initiated by the transmitting
device after the last byte is transferred. An example of a write cycle can be found in Figure 75 and Figure 76.
Note that the THS7303 does not allow multiple write transfers to occur. See the Example: Writing to the
THS7303 section for the proper procedure on writing to the THS7303.
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