Datasheet
Table Of Contents
- FEATURES
- APPLICATIONS
- DESCRIPTION
- DESCRIPTION (continued)
- ABSOLUTE MAXIMUM RATINGS
- DISSIPATION RATINGS
- RECOMMENDED OPERATING CONDITIONS
- ELECTRICAL CHARACTERISTICS: VS+ = 3.3 V
- ELECTRICAL CHARACTERISTICS: VS+ = 5 V
- TIMING REQUIREMENTS
- FUNCTIONAL BLOCK DIAGRAM
- PIN CONFIGURATION
- TYPICAL CHARACTERISTICS
- TYPICAL CHARACTERISTICS: VS+ = 3.3 V
- TYPICAL CHARACTERISTICS: VS+ = 5 V
- APPLICATION INFORMATION
- OPERATING VOLTAGE
- INPUT OVERVOLTAGE PROTECTION
- TYPICAL CONFIGURATION and VIDEO TERMINOLOGY
- INPUT MODES OF OPERATION: DC
- INPUT MODES OF OPERATION: DC + 135-mV SHIFT
- INPUT MODES OF OPERATION: AC BIAS
- INPUT MODES OF OPERATION: AC SYNC-TIP-CLAMP
- OUTPUT MODES OF OPERATION: DC COUPLED
- OUTPUT MODES OF OPERATION: AC-COUPLED
- OUTPUT MODES OF OPERATION: AC-COUPLED WITH SAG CORRECTION
- INCREASING GAIN
- LOW-PASS FILTER AND BYPASS MODES
- BENEFITS OF THS7303 OVER PASSIVE FILTERING
- I2C INTERFACE NOTES
- GENERAL I2C PROTOCOL
- I2C DESIGN NOTES: ISSUES AND SOLUTIONS
- SLAVE ADDRESS
- CHANNEL SELECTION REGISTER DESCRIPTION (SUB-ADDRESS)
- CHANNEL REGISTER BIT DESCRIPTIONS
- EXAMPLE: WRITING TO THE THS7303
- EXAMPLE: READING FROM THE THS7303
- EVALUATION MODULE
- EVM BOARD LAYERS
- Revision History

17
20
19
18
GND
16
CH.2 IN B
CH.3 IN B
15
I2C-A0
SDA
V
S +
11
14
13
12
SCL
CH.3 SAG
I2C-A1
CH.1 IN B
CH.2 IN A
CH.3 IN A
CH.1 IN A
NC
CH.3 OUT
CH.2 SAG
CH.2 OUT
CH.1 SAG
CH.1 OUT
NC
1
2
3
4
5
6
7
8
9
10
+
+
+
+
External
Input
External
Input
DAC /
Encoder
CVBS
CBVS
17
20
19
18
GND
16
CH.2 IN B
CH.3 IN B
15
I2C-A0
SDA
V
S+
11
14
13
12
SCL
CH. 3 SAG
I2C-A1
CH.1 IN B
CH.2 IN A
CH.3 IN A
CH.1 IN A
NC
CH.3 OUT
CH. 2 SAG
CH.2 OUT
CH. 1 SAG
CH.1 OUT
NC
1
2
3
4
5
6
7
8
9
10
+
+
+
THS7303
THS7313
75 W
75 W
75 W
75 W
75 W
75 W
75 W75 W
75 W
75 W
75 W
75 W
75 W
75 W
75 W
75 W
75 W
75 W
R
(130 W)
R
(130 W)
R
(130 W)
R
(130 W)
R
(130 W)
R
(130 W)
Y’
Out
P’
Out
B
P’
Out
R
P’
R
P’
R
P’
B
P’
B
Y’
Y’
C’
Out
Y’
Out
S-Video
S-VideoC’
S-Video
C’
S-Video
Y’
S-Video Y’
CBVS
Out
470 F
(SeeNote A)
m
470 F
(SeeNote A)
m
470 F
(SeeNote A)
m
100 Fm0.01 Fm
1 Fm
0.1 Fm
1 Fm
0.1 Fm
0.1 Fm
0.1 Fm
3.3V
3.3V
470 Fm
(SeeNote A)
470 Fm
(SeeNote A)
0.1 Fm
0.1 Fm
3.3V
100 Fm
I C
Controller
2
I C
Controller
2
I C Address=0101100
2
I C Address=0101110
2
ACSTC
ACSTC
ACSTC
ACBias
ACBias
+V
S
ACBias
DC+135mV
DC+135mV
DC+135mV
DC+135mV
DC+135mV
DC+135mV
THS7303
SLOS479B – OCTOBER 2005– REVISED MARCH 2011
www.ti.com
A. Due to the high frequency content of the video signal, it is recommended, but not required, to add a 0.01-μF capacitor
in parallel with these large capacitors.
Figure 70. Typical 6-Channel SDTV/EDTV/HDTV Encoder Interfacing to a THS7303 and a THS7313
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