Datasheet
Table Of Contents
- FEATURES
- APPLICATIONS
- DESCRIPTION
- DESCRIPTION (continued)
- ABSOLUTE MAXIMUM RATINGS
- DISSIPATION RATINGS
- RECOMMENDED OPERATING CONDITIONS
- ELECTRICAL CHARACTERISTICS: VS+ = 3.3 V
- ELECTRICAL CHARACTERISTICS: VS+ = 5 V
- TIMING REQUIREMENTS
- FUNCTIONAL BLOCK DIAGRAM
- PIN CONFIGURATION
- TYPICAL CHARACTERISTICS
- TYPICAL CHARACTERISTICS: VS+ = 3.3 V
- TYPICAL CHARACTERISTICS: VS+ = 5 V
- APPLICATION INFORMATION
- OPERATING VOLTAGE
- INPUT OVERVOLTAGE PROTECTION
- TYPICAL CONFIGURATION and VIDEO TERMINOLOGY
- INPUT MODES OF OPERATION: DC
- INPUT MODES OF OPERATION: DC + 135-mV SHIFT
- INPUT MODES OF OPERATION: AC BIAS
- INPUT MODES OF OPERATION: AC SYNC-TIP-CLAMP
- OUTPUT MODES OF OPERATION: DC COUPLED
- OUTPUT MODES OF OPERATION: AC-COUPLED
- OUTPUT MODES OF OPERATION: AC-COUPLED WITH SAG CORRECTION
- INCREASING GAIN
- LOW-PASS FILTER AND BYPASS MODES
- BENEFITS OF THS7303 OVER PASSIVE FILTERING
- I2C INTERFACE NOTES
- GENERAL I2C PROTOCOL
- I2C DESIGN NOTES: ISSUES AND SOLUTIONS
- SLAVE ADDRESS
- CHANNEL SELECTION REGISTER DESCRIPTION (SUB-ADDRESS)
- CHANNEL REGISTER BIT DESCRIPTIONS
- EXAMPLE: WRITING TO THE THS7303
- EXAMPLE: READING FROM THE THS7303
- EVALUATION MODULE
- EVM BOARD LAYERS
- Revision History

17
20
19
18
GND
16
CH.2 IN B
CH.3 IN B
15
I2C-A0
SDA
V
S+
11
14
13
12
SCL
CH.3 SAG
I2C-A1
CH.1 IN B
CH.2 IN A
CH.3 IN A
CH.1 IN A
NC
CH.3 OUT
CH.2 SAG
CH.2 OUT
CH.1 SAG
CH.1 OUT
NC
1
2
3
4
5
6
7
8
9
10
+
+
+
+
S-Video
Y’
S-Video
C’
CVBS
Y’
P’
B
P’
R
R
R
R
R
R
R
DAC /
Encoder
3.3V
75 W
75 W
75 W
75 W
75 W
75 W
Video
Out1
Video
Out2
Video
Out3
0.01 Fm
+Vs
100 Fm
330 Fm
(SeeNote A)
330 Fm
(SeeNote A)
330 Fm
(SeeNote A)
I C
Controller
2
DC+135mV
DC+135mV
DC+135mV
DC+135mV
DC+135mV
DC+135mV
THS7303
www.ti.com
SLOS479B –OCTOBER 2005– REVISED MARCH 2011
The I
2
C interface of the THS7303 allows each channel to be configured totally independent of the other
channels. One of the benefits is that a multiple output encoder (or DAC) can be routed through one THS7303
with the proper input configuration and low-pass filter required regardless of the signal. This is useful for a
portable system or in a low-cost system where only one set (or two sets in parallel) is desired on the output of
the system. An update of the I
2
C commands changes the THS7303 channels. An example is shown in Figure 69
where the input MUX allows for one set of HDTV signals to be put into the THS7303, and then through an I
2
C
update, a SDTV set of signals is sent through the THS7303 with the proper input mode and low-pass filters.
A. Due to the high frequency content of the video signal, it is recommended, but not required, to add a 0.01-μF capacitor
in parallel with these large capacitors.
Figure 69. Typical SD/ED/ and HD Video and SDTB Encoder DAC Driving a Single THS7303
Although the circuit of Figure 69 conserves space and cost, the reuse of the output connections may not be the
best solution. For a complete 6-channel system, it is better to use the THS7303 and the THS7313 (see
SLOS483) together, as shown in Figure 70. The THS7313 is targeted for SDTV signals and is limited to an
8-MHz filter. As discussed in the I
2
C section, it is easy to have both parts in one system because the I
2
C address
of each part can be one of four discrete addresses by the logic appearing on the I
2
C-A1 and I
2
C-A0 lines.
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