Datasheet
Table Of Contents
- FEATURES
- APPLICATIONS
- DESCRIPTION
- DESCRIPTION (continued)
- ABSOLUTE MAXIMUM RATINGS
- DISSIPATION RATINGS
- RECOMMENDED OPERATING CONDITIONS
- ELECTRICAL CHARACTERISTICS: VS+ = 3.3 V
- ELECTRICAL CHARACTERISTICS: VS+ = 5 V
- TIMING REQUIREMENTS
- FUNCTIONAL BLOCK DIAGRAM
- PIN CONFIGURATION
- TYPICAL CHARACTERISTICS
- TYPICAL CHARACTERISTICS: VS+ = 3.3 V
- TYPICAL CHARACTERISTICS: VS+ = 5 V
- APPLICATION INFORMATION
- OPERATING VOLTAGE
- INPUT OVERVOLTAGE PROTECTION
- TYPICAL CONFIGURATION and VIDEO TERMINOLOGY
- INPUT MODES OF OPERATION: DC
- INPUT MODES OF OPERATION: DC + 135-mV SHIFT
- INPUT MODES OF OPERATION: AC BIAS
- INPUT MODES OF OPERATION: AC SYNC-TIP-CLAMP
- OUTPUT MODES OF OPERATION: DC COUPLED
- OUTPUT MODES OF OPERATION: AC-COUPLED
- OUTPUT MODES OF OPERATION: AC-COUPLED WITH SAG CORRECTION
- INCREASING GAIN
- LOW-PASS FILTER AND BYPASS MODES
- BENEFITS OF THS7303 OVER PASSIVE FILTERING
- I2C INTERFACE NOTES
- GENERAL I2C PROTOCOL
- I2C DESIGN NOTES: ISSUES AND SOLUTIONS
- SLAVE ADDRESS
- CHANNEL SELECTION REGISTER DESCRIPTION (SUB-ADDRESS)
- CHANNEL REGISTER BIT DESCRIPTIONS
- EXAMPLE: WRITING TO THE THS7303
- EXAMPLE: READING FROM THE THS7303
- EVALUATION MODULE
- EVM BOARD LAYERS
- Revision History
Input
Pin
Input
Internal
Circuitry
V
S+
THS7303
SLOS479B – OCTOBER 2005– REVISED MARCH 2011
www.ti.com
INPUT MODES OF OPERATION: DC
The inputs to the THS7303 allows for both ac-coupled and dc-coupled inputs. Many DACs or video encoders can
be dc-connected to the THS7303. However, one of the drawbacks to dc coupling is when 0 V is applied to the
input of the THS7303. Although the input of the THS7303 allows for a 0-V input signal, the output swing of the
THS7303 cannot yield a 0-V signal. This applies to any traditional single-supply amplifier because of the
limitations of the output transistors. Both CMOS and bipolar transistors cannot go to 0 V while sinking a
significant amount of current. This trait of a transistor is also the same reason why the highest output voltage is
always less than the power-supply voltage when sourcing a significant amount of current.
The internal gain is fixed at 6 dB (2 V/V) regardless of the configuration of the THS7303, and dictates what the
allowable linear input voltage range is without clipping concerns. For example, if the power supply is set to 3 V,
the maximum output is about 2.9 V. Thus, to avoid clipping, the allowable input is 2.9 V / 2 = 1.45 V. This is true
for up to the maximum recommended 5-V power supply that allows about a 4.9 V / 2 = 2.45 V input range while
avoiding clipping on the output.
The input impedance of the THS7303 in this mode of operation is > 1 MΩ. This is a result of the input buffer
being configured as a unity gain amplifier, as shown in Figure 60.
Figure 60. Equivalent DC Input Mode Circuit
The input stage of the THS7303 is designed with PNP bipolar transistors. There is a finite amount of bias current
flowing out of the THS7303 input pin. This bias current (typically about 0.6 μA), must have a path to flow or else
the input stage voltage increases. For example, if there is a 1-MΩ resistance to ground on the input node, the
resulting voltage appearing at the input node is 0.6 μA x 1 MΩ = 0.6 V. Therefore, it should be noted that if a
channel is powered on and has no input termination, the input bias current causes the input stage to float high
until saturation of the input stage exists, approximately 1.4 V from the power supply. Typically, this is not a
concern because most terminations result in an equivalent source impedance of 37.5 Ω to 300 Ω.
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