Datasheet

17
20
19
18
GND
16
CH.2 IN B
CH.3 IN B
15
I2C-A0
SDA
V
S+
11
14
13
12
SCL
CH. 3 SAG
I2C-A1
CH.1 IN B
CH.2 IN A
CH.3 IN A
CH.1 IN A
NC
CH.3 OUT
CH. 2 SAG
CH.2 OUT
CH. 1 SAG
CH.1 OUT
NC
DAC /
Encoder
(THS8200)
3.3V
1
2
3
4
5
6
7
8
9
10
Y’
P’
B
P’
R
External
Input
Y’
P’
B
P’
R
75 W
75 W
75 W
75 W
75 W
75 W
75 W
75 W
75 W
0.1 Fm
0.01 Fm
100 Fm
1 Fm
1 Fm
R
R
R
Y’
Out
470 Fm
470 Fm
470 Fm
(SeeNote A)
(SeeNote A)
(SeeNote A)
P’
B
Out
P’
R
Out
+
+
+
+
+Vs
I C
Controller
2
HDTV
480i
576i
480p
576p
720p
1080i
1080p
ACSTC
ACBias
ACBias
DC+135mV
DC+135mV
DC+135mV
THS7303
www.ti.com SLOS479B –OCTOBER 2005– REVISED MARCH 2011
placed first in the system. Since the blue color difference channel (P'
B
) is next and the red color difference
channel (P'
R
) is last, then it also makes logical sense to place the B' signal on the second channel and the R'
signal on the third channel respectfully. Thus hardware compatibility is better achieved when using G'B'R' rather
than R'G'B'. Note that for many G'B'R' systems sync is embeded on all three channels, but may not always be
the case in all systems.
A. Due to the high frequency content of the video signal, it is recommended, but not required, to add a 0.01-μF capacitor
in parallel with these large capacitors.
Figure 59. Typical Y'P'
B
P'
R
Inputs From DC-Coupled Encoder/DAC and
AC-Coupled External Inputs With AC-Coupled Line Driving
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