Datasheet

Description
1-3
General Information
Figure 1–1. THS7002 Evaluation Module
PGA – A
Output
R45
PGA – B
Output
C21L2C5C4L1
+V
CC
GND
+5 V–V
CC
Pre-Amp A
Output
Pre-Amp B
Output
Input B
J7
B
J8
C20
JP5
J10
J9
C3
R4
R3
U2
C2
R1C1 R2
R9
Input A
J6
J5
R24
R26
R28
R30
R32
C18
C19
R34
R36
R38
R40
R42
R44
R18 R5
U1
AG2
(3)
AG1
(2)
AG0
(1)
S1
S2
VH
(6)
BVREF
(5)
BS/D
(4)
AS/D
(4)
AVREF
(5)
VL
(6)
BG2
(1)
BG1
(2)
BG0
(3)
JP4JP3
R16
R17
C17
JP1
R6
C6
R20
C7
C11
C12
R12
C13
C10
R11
R15
R14
R13
R35
R37
R39
R41
R23
R25
R27
R29
R11
R33
R10
C9
JP2
C14
1998
Texas Instruments
J4J3
J2
J1
SLOP136
Rev. B
THS7002 EVM Board
+++
R7
R8
C8
GND
U2 Out
1
1
1
1
1
Input power is applied to the EVM through banana jacks J1, J2, J3, and J4. An
LC filter on each power bus isolates the EVM circuits from the external supply
(Figure 1–2). J4 provides a reference point for numerous circuit functions and
draws relatively little current. The schematic for the EVM amplifiers appears
in Figure 1–3.
Figure 1–2. THS7002 EVM Power Conditioning Schematic Diagram
–15 V
L1
0.22 µH
C4
6.8 µF
15 V
J1
V
CC
+
J2
GND
+
J3
–V
CC
+
J4
5 V
5 V
L2
0.22 µH
C5
6.8 µF
C21
6.8 µF
TP1