Datasheet

DISTORTION PERFORMANCE
DRIVING CAPACITIVE LOADS
THS6214
SBOS431 – MAY 2009 ....................................................................................................................................................................................................... www.ti.com
resistor is shorted to ground. However, shorting the capacitive loads greater than 2pF can begin to
output pin directly to the adjacent positive degrade device performance. Long printed-circuit
power-supply pin (24-pin package), in most cases, board (PCB) traces, unmatched cables, and
destroys the amplifier. If additional short-circuit connections to multiple devices can easily cause this
protection is required, a small series resistor may be value to be exceeded. Always consider this effect
included in the supply lines. Under heavy output carefully, and add the recommended series resistor
loads, this additional resistor reduces the available as close as possible to the THS6214 output pin (see
output voltage swing. A 5 Ω series resistor in each the Board Layout Guidelines section).
power-supply lead limits the internal power
dissipation to less than 1W for an output short-circuit,
while decreasing the available output voltage swing
The THS6214 provides good distortion performance
only 0.5V for up to 100mA desired load currents.
into a 100 Ω load on ± 12V supplies. Relative to
Always place the 0.1 µ F power-supply decoupling
alternative solutions, the amplifier provides
capacitors after these supply current limiting resistors,
exceptional performance into lighter loads and/or
directly on the supply pins.
operation on a dual ± 6V supply. Generally, until the
fundamental signal reaches very high frequency or
power levels, the second harmonic dominates the
One of the most demanding and yet very common distortion with a negligible third-harmonic component.
load conditions for an op amp is capacitive loading. Focusing then on the second harmonic, increasing
Often, the capacitive load is the input of an the load impedance improves distortion directly.
ADC — including additional external capacitance that Remember that the total load includes the feedback
may be recommended to improve the ADC linearity. network — in the noninverting configuration (see
A high-speed, high open-loop gain amplifier such as Figure 81 ), this value is the sum of R
F
+ R
G
, whereas
the THS6214 can be very susceptible to decreased in the inverting configuration it is just R
F
. Also,
stability and closed-loop response peaking when a providing an additional supply decoupling capacitor
capacitive load is placed directly on the output pin. (0.01 µ F) between the supply pins (for bipolar
When the amplifier open-loop output resistance is operation) improves the second-order distortion
considered, this capacitive load introduces an slightly (from 3dB to 6dB).
additional pole in the signal path that can decrease
In most op amps, increasing the output voltage swing
the phase margin. Several external solutions to this
directly increases harmonic distortion. The Typical
problem have been suggested.
Characteristics show the second harmonic increasing
When the primary considerations are frequency at a little less than the expected 2x rate, whereas the
response flatness, pulse response fidelity, and/or third harmonic increases at a little less than the
distortion, the simplest and most effective solution is expected 3x rate. Where the test power doubles, the
to isolate the capacitive load from the feedback loop difference between it and the second harmonic
by inserting a series isolation resistor between the decreases less than the expected 6dB, whereas the
amplifier output and the capacitive load. This series difference between it and the third harmonic
resistor does not eliminate the pole from the loop decreases by less than the expected 12dB. This
response, but shifts it and adds a zero at a higher difference also shows up in the two-tone, third-order
frequency. The additional zero acts to cancel the intermodulation spurious (IM3) response curves. The
phase lag from the capacitive load pole, thus third-order spurious levels are extremely low at
increasing the phase margin and improving stability. low-output power levels. The output stage continues
The Typical Characteristics show the recommended to hold them low even as the fundamental power
R
S
vs Capacitive Load (see Figure 6 , Figure 24 , reaches very high levels.
Figure 36 , Figure 48 , Figure 61 , and Figure 73 ) and
the resulting frequency response at the load. Parasitic
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