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FEATURES DESCRIPTION

TYPICAL ADSL CO-LINE DRIVER CIRCUIT

APPLICATIONS

−

THS6182a

+12 V

−12 V

−

1:1.2

−12 V

+12V

8.68 Ω

100

Ω

1 k

Ω

1 k

Ω

1.33 kΩ

1.33 kΩ953 Ω

CODEC

IN−

CODEC

IN+

8.68

Ω

20-dBm

Line

Power

THS6182b

THS6182

SLLS544H – SEPTEMBER 2002 – REVISED JUNE 2007

LOW-POWER DISSIPATION ADSL LINE DRIVER

• Low-Power Dissipation Increases ADSL Line

The THS6182 is a current feedback differential line

Card Density

driver ideal for full rate ADSL systems. Its extremely

low-power dissipation is ideal for ADSL systems that

• Low THD of -88 dBc (100 Ω , 1 MHz)

must achieve high densities in ADSL central office

• Low MTPR Driving +20 dBm on the Line

rack applications. The unique architecture of the

– -76 dBc With High Bias Setting

THS6182 allows the quiescent current to be much

lower than existing line drivers while still achieving

– -74 dBc With Low Bias Setting

high linearity without the need for excess open loop

• Wide Output Swing of 44 V

Differential Into

gain. Fixed multiple bias settings of the amplifiers

a 200- Ω Differential Load (V

= ± 12 V)

allow for enhanced power savings for line lengths

• High Output Current of 600 mA (Typ)

where the full performance of the amplifier is not

required. To allow for even more flexibility and power

• Wide Supply Voltage Range of ± 5 V to ± 15 V

savings, an I

ADJ

pin is available to further lower the

• Pin Compatible with EL1503C and EL1508C

bias currents while maintaining stable operation with

– Multiple Package Options

as little as 1.8 mA per channel. The wide output

swing of 44 V

differentially with ± 12-V power

• Multiple Power Control Modes

supplies allows for more dynamic headroom, keeping

– 11 mA/ch Full Bias Mode

distortion at a minimum. With a low 3.2 nV/ √ Hz

– 7.5 mA/ch Mid Bias Mode

voltage noise coupled with a low 10 pA/ √ Hz inverting

– 4 mA/ch Low Bias Mode

current noise, the THS6182 increases the sensitivity

of the receive signals, allowing for better margins

– 0.25 mA/ch Shutdown Mode

and reach.

– I

ADJ

Pin for User Controlled Bias Current

– Stable Operation Down to 1.8 mA/ch

USING ACTIVE IMPEDANCE

• Low Noise for Increased Receiver Sensitivity

– 3.2 nV/ √ Hz Voltage Noise

– 1.5 pA/ √ Hz Noninverting Current Noise

– 10 pA/ √ Hz Inverting Current Noise

• Ideal for Full Rate ADSL Applications

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PowerPAD is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (38 pages)

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THS6182 www.ti.
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THS6182 www.ti.com SLLS544H – SEPTEMBER 2002 – REVISED JUNE 2007 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
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THS6182 www.ti.com SLLS544H – SEPTEMBER 2002 – REVISED JUNE 2007 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted (1) ELECTRICAL THS6132 ±16.
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THS6182 www.ti.com SLLS544H – SEPTEMBER 2002 – REVISED JUNE 2007 ELECTRICAL CHARACTERISTICS (continued) over recommended operating free-air temperature range, TA = 25°C, VCC = ±12 V, RF = 2 kΩ, Gain = +5, IADJ = Bias1 = Bias2 = 0 V, RL = 50 Ω (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP RL = 100 Ω ±3.9 ±4.1 RL = 25 Ω ±3.7 ±3.9 RL = 100 Ω ±10.7 ±11 ±10 ±10.6 RL = 100 Ω ±13.5 ±13.9 RL = 25 Ω ±12.7 ±13.
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THS6182 www.ti.com SLLS544H – SEPTEMBER 2002 – REVISED JUNE 2007 ELECTRICAL CHARACTERISTICS (continued) over recommended operating free-air temperature range, TA = 25°C, VCC = ±12 V, RF = 2 kΩ, Gain = +5, IADJ = Bias1 = Bias2 = 0 V, RL = 50 Ω (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX 1 20 UNIT DC PERFORMANCE TA = 25°C Input offset voltage VOS TA = full range VCC = ±5 V, ±12 V, ±15 V Differential offset voltage 0.
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THS6182 www.ti.com SLLS544H – SEPTEMBER 2002 – REVISED JUNE 2007 RG 750 Ω +18 V 4.87 Ω − CODEC + V IN+ THS6182a 1 kW RG 1.33 kW 1:1.6 20-dBm Line Power 100 Ω 1 kW RF 750 Ω +18 V 4.87 Ω − CODEC + V IN− THS6182b Figure 1. Single-Supply ADSL CO Line Driver Circuit Utilizing Active Impedance (SF = 4) PIN ASSIGNMENTS 19 D2 OUT VCC − 3 18 VCC + 17 GND GND GND A.
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THS6182 www.ti.
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THS6182 www.ti.com SLLS544H – SEPTEMBER 2002 – REVISED JUNE 2007 LARGE SIGNAL OUTPUT AMPLITUDE vs FREQUENCY Large Signal Output Amplitude −dB(VPP ) 15 M id Bias Mo de 10 Lo w Bias Mo de 0 10 0 VO = 0.5 VPP −6 −12 VO = 0.25 VPP −18 100 k 1M 10 M 100 M f − Frequency − Hz VO = 2 VPP 6 VO = 1 VPP VO = 0.5 VPP −6 In− 10 0 100 10 10 Vn In+ 1 10 1M 10 M 100 M f f − Frequency − Hz 3 15 VCC= ±12 V Gain = 5 RL= 100 Ω 10 1 5 0 0 Vin −1 −5 −2 1 100 k −10 Vo ut −3 −15 0 .0 0 .5 1.
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THS6182 www.ti.com SLLS544H – SEPTEMBER 2002 – REVISED JUNE 2007 OUTPUT AMPLITUDE vs FRQUENCY OUTPUT AMPLITUDE vs FREQUENCY 16 16 15 15 RF = 750 RF = 500 21 RF = 750 RF = 500 RF = 1 k 12 11 RF = 2 k 10 VCC = ±15 V Gain = 5 RL = 25 Ω VO = 0.1 Vrms Full Bias 9 8 7 100 k 13 12 11 10 9 8 1M 10 M 100 M f − Frequency − Hz VCC = ±15 V Gain = 5 RL = 100 Ω VO = 0.
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THS6182 www.ti.com SLLS544H – SEPTEMBER 2002 – REVISED JUNE 2007 OUTPUT AMPLITUDE vs FREQUENCY OUTPUT AMPLITUDE vs FREQUENCY 16 RF = 500 RF = 2 k 11 VCC = ±12 V Gain = 5 RL = 25 Ω VO = 0.1 Vrms Mid Bias 7 100 k RF = 2 k 11 VCC = ±12 V Gain = 5 RL = 25 Ω VO = 0.1 Vrms Low Bias 10 7 100 k RF = 2 k VCC = ±12 V Gain = 5 RL = 100 Ω VO = 0.1 Vrms Mid Bias 15 20 14 19 13 RF = 500 11 9 8 1M 10 M f − Frequency − Hz RF = 1 k 12 10 RF = 2 k VCC = ±12 V Gain = 5 RL = 100 Ω VO = 0.
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THS6182 www.ti.com SLLS544H – SEPTEMBER 2002 – REVISED JUNE 2007 OUTPUT AMPLITUDE vs FREQUENCY 3 RF = 1.2 k 2 RF = 1 k 0 −1 RF = 2 k −2 VCC = ±5 V Gain = 1 RL = 25 Ω VO = 0.1 Vrms Full Bias −3 −4 −5 −6 100 k 1M RF = 2 k −2 −3 VCC = ±5 V Gain = 1 RL = 100 Ω VO = 0.1 Vrms Full Bias −5 −6 100 k 1G RF = 750 14 0 −1 −4 10 M 100 M f − Frequency − Hz RF = 500 15 RF = 1.
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THS6182 www.ti.com SLLS544H – SEPTEMBER 2002 – REVISED JUNE 2007 QUIESCENT CURRENT vs TEMPERATURE COMMON-MODE REJECTION RATIO vs COMMON-MODE VOLTAGE 25 13 90 Vcc = +/−15 V Common−Mode Rejection Ratio −dB Icc+ (Full) Icc− (Full) 20 Icc+ (Mid) 15 Icc− (Mid) 10 Icc+ (Low) Icc− (Low) Icc− (SD) 5 Icc+ (SD) −20 12 −40 Deg C 70 85 Deg C 60 25 Deg C 50 40 30 0 20 40 60 Temperature − Deg.
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THS6182 www.ti.
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THS6182 www.ti.
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THS6182 www.ti.com SLLS544H – SEPTEMBER 2002 – REVISED JUNE 2007 3RD HARMONIC DISTORTION vs OUTPUT VOLTAGE −65 Differential configuration −70 Low Bias Mid Bias 3rd HD −dBc −75 −80 −85 −90 Full Bias −95 VCC = ±5 V Gain = 5 RL = 50 Ω RF = 1 kΩ f = 1 MHz −100 0 2 4 6 Output Voltage − Vpp 8 10 Figure 68.
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THS6182 www.ti.com SLLS544H – SEPTEMBER 2002 – REVISED JUNE 2007 APPLICATION INFORMATION The THS6182 contains two independent operational amplifiers. These amplifiers are current feedback topology amplifiers made for high-speed operation. They have been specifically designed to deliver the full power requirements of ADSL and therefore can deliver output currents of at least 400 mA at full output voltage. The THS6182 is fabricated using Texas Instruments 30-V complementary bipolar process, HVBiCOM.
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THS6182 www.ti.com SLLS544H – SEPTEMBER 2002 – REVISED JUNE 2007 APPLICATION INFORMATION (continued) RECOMMENDED FEEDBACK AND GAIN RESISTOR VALUES As with all current feedback amplifiers, the bandwidth of the THS6182 is an inversely proportional function of the value of the feedback resistor. The recommended resistors with a ±12-V power supply for the optimum frequency response with a 25-Ω load system is 1 kΩ for a gain of 5.
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THS6182 www.ti.com SLLS544H – SEPTEMBER 2002 – REVISED JUNE 2007 APPLICATION INFORMATION (continued) eRs RS en Noiseless + _ eni eno IN+ IN− eRf RF eRg RG Figure 71. Noise Model The total equivalent input noise density (eni) is calculated by using the following equation: e Where: ni + Ǹ ǒenǓ ) ǒIN ) 2 R Ǔ S 2 ǒ ) IN– ǒR F ø R G ǓǓ 2 ǒ ) 4 kTRs ) 4 kT R ø R F G Ǔ k = Boltzmann’s constant = 1.
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THS6182 www.ti.com SLLS544H – SEPTEMBER 2002 – REVISED JUNE 2007 APPLICATION INFORMATION (continued) 1 kΩ 1 kΩ Input _ 2Ω Output THS6182 + CLOAD Figure 72. Driving a Capacitive Load PCB DESIGN CONSIDERATIONS Proper PCB design techniques in two areas are important to assure proper operation of the THS6182. These areas are high-speed layout techniques and thermal-management techniques. Because the THS6182 is a high-speed part, the following guidelines are recommended.
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THS6182 www.ti.com SLLS544H – SEPTEMBER 2002 – REVISED JUNE 2007 APPLICATION INFORMATION (continued) heat transfer during soldering operations. This makes the soldering of vias that have plane connections easier. However, in this application, low thermal resistance is desired for the most efficient heat transfer. Therefore, the holes under the THS6182 package should make their connection to the internal ground plane with a complete connection around the entire circumference of the plated through hole. 6.
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THS6182 www.ti.com SLLS544H – SEPTEMBER 2002 – REVISED JUNE 2007 APPLICATION INFORMATION (continued) 0.4953 0.1905 Pad size 24 x (0.3048 x 0.762) mm 0.3721 0.1905 0.4953 2.2987 0.3641 4.9022 3.302 5.9182 PowerPAD and Via layout (Pad size 3.65 mm x 2.65 mm , 9 Vias with diameter = 0.254 mm) 0.682 1.143 0.563 2.65 0.762 3.65 Vias should go through the board connecting the top layer PowerPAD to any and all ground planes. The larger the ground plane, the more area to distribute the heat.
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THS6182 www.ti.com SLLS544H – SEPTEMBER 2002 – REVISED JUNE 2007 APPLICATION INFORMATION (continued) ǒ T P D + –T MAX A q JA Ǔ Where: PD TMAX TA θJA = Maximum power dissipation of THS6182 (watts) = Absolute maximum operating junction temperature (125°C) = Free-ambient air temperature (°C) = θJC + θCA θJC = Thermal coefficient from junction to case. See the Package Dissipation Ratings table. θCA = Thermal coefficient from case to ambient determined by PCB layout and construction.
PAGE 23
THS6182 www.ti.com SLLS544H – SEPTEMBER 2002 – REVISED JUNE 2007 APPLICATION INFORMATION (continued) C1 + _ VI R1 R1 = R2 = R C1 = C2 = C Q = Peaking Factor (Butterworth Q = 0.707) R2 f C2 RG RF –3dB RG = + ( 1 2pRC RF 1 2− Q ) Figure 76. 2-Pole Low-Pass Sallen-Key Filter EVALUATION BOARD An evaluation board is available for the THS6182. This board has been configured for proper thermal management of the THS6182.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
PAGE 26
PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant THS6182DWPR SO Power PAD DWP 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.0 Q1 THS6182RHFR VQFN RHF 24 3000 330.0 12.4 4.3 5.3 1.3 8.0 12.0 Q1 THS6182RHFT VQFN RHF 24 250 180.0 12.4 4.3 5.3 1.3 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) THS6182DWPR SO PowerPAD DWP 20 2000 367.0 367.0 45.0 THS6182RHFR VQFN RHF 24 3000 338.1 338.1 20.6 THS6182RHFT VQFN RHF 24 250 210.0 185.0 35.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.