THS6043EVM User’s Guide August 2002 High Performance Linear Products SLOU139
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.
EVM IMPORTANT NOTICE Texas Instruments (TI) provides the enclosed product(s) under the following conditions: This evaluation kit being sold by TI is intended for use for ENGINEERING DEVELOPMENT OR EVALUATION PURPOSES ONLY and is not considered by TI to be fit for commercial use.
EVM WARNINGS AND RESTRICTIONS It is important to operate this EVM within the input voltage ranges described in the EVM User’s Guide. Exceeding the specified input range may cause unexpected operation and/or irreversible damage to the EVM. If there are questions concerning the input range, please contact a TI field representative prior to connecting the input power. Applying loads outside of the specified output range may result in unintended operation and/or possible permanent damage to the EVM.
Information About Cautions and Warnings Preface About This Manual This manual provides information about the EVM used to evaluate the THS6043 high-speed amplifier. Additionally, this document provides a good example of PCB design for high-speed applications. The user should keep in mind the following points. It is recommended that the user initially review the data sheet of the device under test.
Related Documentation From Texas Instruments This is an example of a warning statement. A warning statement describes a situation that could potentially cause harm to you. The information in a caution or a warning is provided for your protection. Please read each caution and warning carefully. FCC Warning This equipment is intended for use in a laboratory test environment only.
Trademarks - Application report (literature number SLOA100), Active Output Imped- ance for ADSL Line Drivers, http://www−s.ti.com/sc/psheets/sloa100/sloa100.pdf Trademarks PowerPAD is a trademark of Texas Instruments.
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Contents 1 Introduction and Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Evaluation Module Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 THS6043EVM Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . .
Contents 1−1 2−1 2−2 3−1 3−2 3−3 3−4 3−5 3−6 3−7 3−8 3−9 3−10 5−1 5−2 5−3 5−4 5−5 Schematic of the Populated Circuit on the EVM (Default Configuration) . . . . . . . . . . . . . . 1-3 Power Supply Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Signal Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 Default Configuration Operation . . . . .
Chapter 1 The Texas Instruments THS6043 evaluation module (EVM) helps designers evaluate the performance of the THS6043 operational amplifier. Also, this EVM is a good example of high-speed PCB design. This document details the THS6043EVM. It includes a list of EVM features, a brief description of the module illustrated with a series of schematic diagrams, EVM specifications, details on connecting and using the EVM, and a discussion of high-speed amplifier design considerations.
Description 1.1 Description The THS6043EVM provides a platform for developing high-speed op amp application circuits. It contains the THS6043 high-speed dual op amp, a number of passive components, and various features and footprints that enable the user to experiment, test, and verify various operational amplifier circuit implementations. The PC board measures 4.21 by 2.88 inches. 1.
EVM Default Configuration Figure 1−1. Schematic of the Populated Circuit on the EVM (Default Configuration) +V J1 IN1 Z1 R23 0 0 14 U1A 3 + THS6043 1 2 − R1 49.9 W 4 TP2 OUT1 TP1 R17 R29 49.9 W 49.9 W R5 750 W −V R25 100 W U1C THS6043 9 5 7 NC SD 15 PWP 8 10 GND R7 210 W J2 IN2 Z2 C3 1 mF U1B R16 THS6043 750 W 12 − R18 13 11 + 49.9 W R24 0 0 R12 49.9 W C10 6 J4 − VCC 0.1 mF +V TP6 C14 JP1 0.1 mF C7 ** C8 ** 0.1 mF 1 mF + C9 1 mF 1 +V 49.9 W C1 + 10 mF C12 R27 4.
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Chapter 2 !" This section describes how to connect the THS6043EVM to test equipment. It is recommended that the user connect the EVM as described in this section to avoid damage to the EVM or the THS6043 installed on the board. Topic Page 2.1 Test Equipment Required . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.2 Power Supply Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.
Test Equipment Required 2.1 Test Equipment Required - Dual dc output power supply (± 15 V, 200 mA output minimum) - Two dc current meters with resolution to 1 mA and capable of the maximum current supplied by the dc power source. Note: Some power supplies incorporate current meters which may be applicable to this test. - 50-Ω source impedance function generator (1 MHz, 10 Vpp sine wave) - Oscilloscope (50 MHz bandwidth minimum, 50-Ω terminated BNC Input) 2.
Input and Output Test Setup (See Figure 2−2) 2.3 Input and Output Test Setup (See Figure 2−2) - Set the function generator to a 1 MHz, ±2.5 V (5 Vpp) sine wave with no dc offset. - Turn off the function generator before proceeding to the next step. - Using a BNC cable, connect the function generator to J1 (IN1 BNC) on the EVM. - Using a BNC cable, connect the oscilloscope to J6 (OUT1 BNC) on the EVM. Set the oscilloscope to 1 V/Division and a time base of 0.2 µSec/Division.
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Chapter 3 !" # Example applications are presented in this chapter. These applications demonstrate the most popular circuits to the user, but many other circuits can be constructed. The user is encouraged to experiment with different circuits, exploring new and creative design techniques. That, after all, is the function of an evaluation board. Topic Page 3.1 Standard Gain Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3.
Standard Gain Configuration 3.1 Standard Gain Configuration The THS6043EVM default configuration is a fully differential input, fully differential output gain stage as shown in Figure 3−1. This gain is calculated according an equation that is similar to the one that describes an instrumentation amplifier: V (diff) + 1 ) 2 R5 Differential gain + O R7 V (diff) I (1) Where: R5 = R16 Series resistors R17 and R18 affect output voltage at J6 and J7.
Single Supply Operation 3.2 Single Supply Operation Many designs use single supply voltages, and the THS6043EVM allows single supply operation. The THS6043EVM can be reconfigured for single supply operation as shown in Figure 3−2. To convert to single supply operation: - Connect ground from the power supply to both J5 (GND) and J4 (−VCC). - Jumper pins 2 and 3 of JP1 together with a jumper plug. This enables connection to a half supply voltage divider. - Populate R4, R14, R20, and R21, with 4.
Active Termination 3.3 Active Termination Active termination is a technique that allows the designer to use a small value resistor for the series resistance (R17 or R18). The circuit then uses positive feedback to make the impedance of this resistor appear much larger, when looking from the line side. This accomplishes two things: 1) A very small resistance is evident when the line driver amplifier transmits signals to the line. This lowers the driver stage output voltage swing range requirement.
Active Termination Now that the return impedance is corrected, forward voltage gain from input to output is calculated. Equation 3 shows the simplified forward gain from Vin to Vo. V " + A + O V V " in ǒ Ǔ ǒ Ǔǒ Ǔ 1) 1– R R F P R F R || R P G R L R )R L S iff R L tt R P (3) Where: R R + LINE L 2 n2 (4) Where n is the turn ratio of the transformer. The reader is cautioned that active termination is a very complex topic, with many considerations.
Snubber Circuit 3.4 Snubber Circuit Figure 3−4. Addition of Snubber Circuit to Active Termination +V J1 IN1 Z1 R23 0 0 R1 TP1 Vo+ 14 U1A THS6043 3 + R17= RS 1 2 − 49.9 W 4 49.9 W <<< Zin J6 Vout+ R5 = RF 750 W −V R6 = RP TP2 Vout+ R7 = 2 RG 210 W V Line 1:n R19 Line = 100 W C5 C3 1 mF TP4 Vout− R11 = RP U1B THS6043 J2 IN2 Z2 R24 0 0 12 − 11 + R16 = RF 750 W R18 = RS 13 <<< Zin J7 Vout− 49.9 W R12 TP3 Vo− 49.
Receive Path Implementation 3.5 Receive Path Implementation Test points TP1 through TP4 are located on the EVM to facilitate the addition of the receive signal path to the signal chain as shown in Figure 3−5. When implementing the receive path, a hybrid must be used since ADSL is full duplex. The hybrid cancels out the TX signal and allows the RX signal from the line to come through. The THS6043EVM does not include receive or hybrid circuitry.
High-Pass Filter 3.6 High-Pass Filter Because ADSL CPE is designed to transmit from 25.875 kHz to 138 kHz, C3 and R7 can be used to implement an HPF function. These are selected to be 20X lower than 25 kHz (1.25 kHz) or so. Some designs use a capacitor—some do not. This path allows for a common gain setting between the two channels. This helps (but does not assure) that the signals are truly differential.
Noninverting Single-Ended Gain Stages 3.7 Noninverting Single-Ended Gain Stages Although ADSL is the obvious application for the THS6043EVM, it can also be configured for other applications.There are component locations on the EVM that allow various dc- and ac-coupled gain stages to be constructed. Referring to Figure 3−7, for example, two dc-coupled noninverting gain stages could be formed by: - Removing R7 and C3 - Making R8 and R9 gain resistors for the two individual stages.
Independent Single-Ended Inverting Gain Stages 3.8 Independent Single-Ended Inverting Gain Stages Two independent inverting gain stages can be created by: - Removing R7, R23, R24, and C3 - Adding zero Ω jumpers at R4 and R14 - Jumper pins 1 and 2 of JP1 - Adding gain resistors (Rg) at R3 and R15. Gain (Av) for each stage is calculated by –Rf / Rg (−R5 / R3 and –R16 / R15). Figure 3−8. Independent Single-Ended Inverting Gain Configuration R5 750 W +V 14 J1 IN1 Z1 R3 2 − 3 + 0 R1 49.
Independent Single-Supply Single-Ended Inverting Gain Stages 3.9 Independent Single-Supply Single-Ended Inverting Gain Stages Two independent inverting gain stages can be created by: - Connecting the –VCC supply (J4) to GND (J5) - Removing R7, R23, R24, and C3 - Addinging zero Ω jumpers at R4 and R14 - Installing 4.99 kΩ resistors at locations R20 and R21 - Jumpering pins 2 and 3 of JP1 - Adding gain resistors (Rg) at R3 and R15.
Shutdown Operation (Channels 1 and 2) divider is formed by R26 and R27, taking the SD input to +V/2, which disables the outputs of the EVM. Please note that due to the low-value input and feedback resistors, some signal leaks from the inputs to the outputs of the EVM. Figure 3−10. Shutdown Operation TP5 SD U1C THS6043 R25 100 W 9 5 SD 15 7 NC PWP 8 10 GND 6 3-12 R26 4.99 kW JP2 R27 4.
Chapter 4 $ #% & ' ( ) * The THS6043EVM layout has been designed for use with high-speed signals and can be used as an example when designing PCBs incorporating the THS6043. Careful attention has been given to component selection, grounding, power supply bypassing, and signal path layout. Disregarding these basic design considerations could result in less than optimum performance of the THS6043 high-speed operational amplifier.
The printed-circuit board that is used with PowerPAD packages must have features included in the design to remove the heat from the package efficiently. As a minimum, there must be an area of solder-tinned-copper underneath the PowerPAD package. This area is called the thermal land. The thermal land varies in size depending on the PowerPAD package being used, the PCB construction, and the amount of heat that needs to be removed.
Chapter 5 !" + This chapter describes the EVM hardware. It includes the EVM parts list, and printed circuit board layout. Table 5−1. THS6043EVM Bill of Materials Item Description Reference Designator PCB QTY Manufacturer’s Part Number Distributor’s Part Number (Steward) HI1206N800R−00 (Digi-Key) 240−1010−1−ND 1 Bead, Ferrite, 3A, 80 Ω, SMD size 1206 FB1, FB2 2 2 Open, size 1206 C5 1 3 Cap, 1.
17 Header, 0.1” centers, 0.025” square pins JP1, JP2 2 (Sullins) PZC36SAAN (Digi-Key) S1011−36−ND 18 Shunts JP1, JP2 2 (Sullins) SSC02SYAN (Digi-Key) S9002−ND 19 Test points (red) TP1 − TP6 6 (Keystone) 5000 (Allied) 839−3600 20 Test points (black) TP7 − TP9 3 (Keystone) 5001 (Allied) 839−3601 21 Jack, banana receptacle, 0.
Figure 5−2.
Figure 5−3.
Figure 5−4.
Figure 5−5. Full Schematic of the THS6043EVM +V 14 Z1 J1 IN1 R23 3 0 0 2 − R4 R1 49.9 W + * 1 4 R7 210 W * R9 * * Z2 R24 0 0 R12 49.9 W 12 − 11 + TP7 TP9 TP6 R20 10 mF * ** 0.1 mF * Not installed ** Install near U1 5-6 * C8 ** 1 mF J7 OUT2 R18 R28 49.9 W 49.9 W TP4 OUT2 J5 GND J4 − VCC FB2 −V C11 C14 JP1 0.1 mF 1 R21 * + 0.1 mF C12 C7 13 0.
