Datasheet

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  ±     
SLOS264G − MARCH 2000 − REVISED DECEMBER 2001
25
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
PCB design considerations (continued)
The next consideration is the package constraints. The two sources of heat within an amplifier are quiescent
power and output power. The designer should never forget about the quiescent heat generated within the
device, especially multiamplifier devices. Because these devices have linear output stages (Class-AB), most
of the heat dissipation is at low output voltages with high output currents. Figure 45 and Figure 46 show this
effect, along with the quiescent heat, with an ambient air temperature of 50°C. Obviously, as the ambient
temperature increases, the limit lines shown will drop accordingly. The area under each respective limit line is
considered the safe operating area. Any condition above this line will exceed the amplifier’s limits and failure
may result. When using V
CC
= ±6 V, there is generally not a heat problem, even with SOIC packages.
However, when using V
CC
= ±12 V, the SOIC package is severely limited in the amount of heat it can dissipate.
The other key factor when looking at these graphs is how the devices are mounted on the PCB. The PowerPAD
devices are extremely useful for heat dissipation. But, the device should always be soldered to a copper plane
to fully use the heat dissipation properties of the PowerPAD. The standard SOIC package, on the other hand,
is highly dependent on how it is mounted on the PCB. As more trace and copper area is placed around the
device, θ
JA
decreases and the heat dissipation capability increases. The currents and voltages shown in these
graphs are for the total package.
Figure 45
10
100
1000
0123456
Both Channels
T
J
= 150°C
T
A
= 50°C
Maximum Output
Current Limit Line
V
CC
= ±6 V
PWP
θ
JA
= 37.5°C/W
DDA
θ
JA
= 45.8°C/W
SO-14 Package
θ
JA
= 67°C/W
High-K Test PCB
SO-8 Package
θ
JA
= 95°C/W
High-K Test PCB
− Maximum RMS Output Current − mA
MAXIMUM RMS OUTPUT CURRENT
vs
RMS OUTPUT VOLTAGE (DUE TO THERMAL LIMITS)
I
O
V
O
− RMS Output Voltage − V
Figure 46
10
100
1000
024681012
Both Channels
T
J
= 150°C
T
A
= 50°C
Maximum Output
Current Limit Line
V
CC
= ±12 V
PWP
θ
JA
= 37.5°C/W
DDA
θ
JA
= 45.8°C/W
SO-14 Package
θ
JA
= 67°C/W
High-K Test PCB
SO-8 Package
θ
JA
= 95°C/W
High-K Test PCB
Safe
Operating
Area
V
O
− RMS Output Voltage − V
MAXIMUM RMS OUTPUT CURRENT
vs
RMS OUTPUT VOLTAGE (DUE TO THERMAL LIMITS)
− Maximum RMS Output Current − mA
I
O