Datasheet


   
 
SLAS201A − DECEMBER 1999 − REVISED SEPTEMBER 2002
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
DAC transfer function
The THS5671A delivers complementary output currents IOUT1 and IOUT2. Output current IOUT1 equals the
approximate full-scale output current when all input bits are set high in mode 0 (straight binary input), i.e. the
binary input word has the decimal representation 16383. For mode 1, the MSB is inverted (twos complement
input format). Full-scale output current will flow through terminal IOUT2 when all input bits are set low (mode
0, straight binary input). The relation between IOUT1 and IOUT2 can thus be expressed as:
IOUT1 + IOUT
FS
* IOUT2
where IOUT
FS
is the full-scale output current. The output currents can be expressed as:
IOUT1 + IOUT
FS
CODE
16384
IOUT2 + IOUT
FS
(16383 * CODE)
16384
where CODE is the decimal representation of the DAC data input word. Output currents IOUT1 and IOUT2 drive
resistor loads R
LOAD
or a transformer with equivalent input load resistance R
LOAD
. This would translate into
single-ended voltages VOUT1 and VOUT2 at terminal IOUT1 and IOUT2, respectively, of:
VOUT1 + IOUT1 R
LOAD
+
CODE
16384
IOUT
FS
R
LOAD
VOUT2 + IOUT2 R
LOAD
+
(16383–CODE)
16384
IOUT
FS
R
LOAD
The differential output voltage VOUT
DIFF
can thus be expressed as:
VOUT
DIFF
+ VOUT1–VOUT2 +
(2CODE–16383)
16384
IOUT
FS
R
LOAD
The latter equation shows that applying the differential output will result in doubling of the signal power delivered
to the load. Since the output currents of IOUT1 and IOUT2 are complementary, they become additive when
processed differentially. Care should be taken not to exceed the compliance voltages at node IOUT1 and
IOUT2, which would lead to increased signal distortion.