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Power and Cabling Requirements

1.3.3 Analog Output

The techniques used in a design of this type are different from those used in lower speed DACs.

Single-ended analog output is derived from the THS56X1A CommsDAC differential outputs IOUT1 and

IOUT2 via a 1:1 RF transformer. A THS3001 operational amplifier (op amp) is a convenient way to derive

a buffered noninverting single-ended output, a buffered inverting single-ended output, or a buffered

differential to single-ended output.

1.4 Power and Cabling Requirements

The EVM dc supply voltages are analog ±5 V and digital 3 V or 5 V. These voltages should be supplied to

the EVM through shielded twisted-pair wire for best performance. This type of power cabling minimizes

any stray or transient pickup from the higher-frequency digital circuitry. If ribbon cables are used for

interfacing to both J1 and J3, the crosstalk between adjacent conductors is minimized if shielded ribbon

cables are used.

1.5 Printed Circuit Assembly as Part of a System

1.5.1 C542/C54xx DSK/Microprocessor Mode

In this mode the DSP or microprocessor supplies data, sample clock, and control signals via J1 and J3,

respectively. W2 is set to positions 1-2, and W1, W3, W5, W6 – W9 are set appropriately (see the User

Configuration section of this document and Figure 1-4).

1.5.2 Pattern Generator Mode

In this mode the pattern generator (Tektronix HFS9009) supplies data and sample clock signals to J1 and

J5, respectively. Shown in Figure 1-2 the mating of the pattern generator adapter and the THS56X1 EVM

connector J1, and control is provided via J3.

SLAU032C– February 2001– Revised April 2011 EVM Overview

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