Datasheet

THS4631
SLOS451B –DECEMBER 2004–REVISED AUGUST 2011 www.ti.com
values dominate the noise of the system. Although performance of the THS4631. Resistors should be
the THS4631 JFET input stage is ideal for a very low reactance type. Surface-mount
high-source impedance because of the low-bias resistors work best and allow a tighter overall
currents, the system noise and bandwidth is limited layout. Again, keep their leads and PC board
by a high-source (R
S
) impedance. trace length as short as possible. Never use
wirebound type resistors in a high frequency
application. Since the output pin and inverting
SLEW RATE PERFORMANCE WITH VARYING
input pins are the most sensitive to parasitic
INPUT STEP AMPLITUDE AND RISE/FALL
capacitance, always position the feedback and
TIME
series output resistors, if any, as close as possible
Some FET input amplifiers exhibit the peculiar
to the inverting input pins and output pins. Other
behavior of having a larger slew rate when presented
network components, such as input termination
with smaller input voltage steps and slower edge
resistors, should be placed close to the
rates due to a change in bias conditions in the input
gain-setting resistors. Even with a low parasitic
stage of the amplifier under these circumstances.
capacitance shunting the external resistors,
This phenomena is most commonly seen when FET
excessively high resistor values can create
input amplifiers are used as voltage followers. As this
significant time constants that can degrade
behavior is typically undesirable, the THS4631 has
performance. Good axial metal-film or
been designed to avoid these issues. Larger
surface-mount resistors have approximately 0.2
amplitudes lead to higher slew rates, as would be
pF in shunt with the resistor. For resistor values >
anticipated, and fast edges do not degrade the slew
2.0 kΩ, this parasitic capacitance can add a pole
rate of the device. The high slew rate of the THS4631
and/or a zero that can effect circuit operation.
allows improved SFDR and THD performance,
Keep resistor values as low as possible,
especially noticeable above 5 MHz.
consistent with load driving considerations.
• Connections to other wideband devices on the
PRINTED-CIRCUIT BOARD LAYOUT
board may be made with short direct traces or
TECHNIQUES FOR OPTIMAL
through onboard transmission lines. For short
PERFORMANCE
connections, consider the trace and the input to
the next device as a lumped capacitive load.
Achieving optimum performance with high frequency
Relatively wide traces (50 mils to 100 mils) should
amplifier-like devices in the THS4631 requires careful
be used, preferably with ground and power planes
attention to board layout parasitic and external
opened up around them. Estimate the total
component types.
capacitive load and determine if isolation resistors
Recommendations that optimize performance include:
on the outputs are necessary. Low parasitic
• Minimize parasitic capacitance to any ac ground
capacitive loads (< 4 pF) may not need an RS
for all of the signal I/O pins. Parasitic capacitance
since the THS4631 is nominally compensated to
on the output and input pins can cause instability.
operate with a 2-pF parasitic load. Higher parasitic
To reduce unwanted capacitance, a window
capacitive loads without an RS are allowed as the
around the signal I/O pins should be opened in all
signal gain increases (increasing the unloaded
of the ground and power planes around those
phase margin). If a long trace is required, and the
pins. Otherwise, ground and power planes should
6-dB signal loss intrinsic to a doubly-terminated
be unbroken elsewhere on the board.
transmission line is acceptable, implement a
matched impedance transmission line using
• Minimize the distance (< 0.25”) from the power
microstrip or stripline techniques (consult an ECL
supply pins to high frequency 0.1-µF and 100-pF
design handbook for microstrip and stripline layout
de-coupling capacitors. At the device pins, the
techniques). A
ground and power plane layout should not be in
50-Ω environment is not necessary onboard, and
close proximity to the signal I/O pins. Avoid
in fact, a higher impedance environment improves
narrow power and ground traces to minimize
distortion as shown in the distortion versus load
inductance between the pins and the de-coupling
plots. With a characteristic board trace impedance
capacitors. The power supply connections should
based on board material and trace dimensions, a
always be de-coupled with these capacitors.
matching series resistor into the trace from the
Larger (6.8 µF or more) tantalum de-coupling
output of the THS4631 is used as well as a
capacitors, effective at lower frequency, should
terminating shunt resistor at the input of the
also be used on the main supply pins. These may
destination device. Remember also that the
be placed somewhat farther from the device and
terminating impedance is the parallel combination
may be shared among several devices in the
of the shunt resistor and the input impedance of
same area of the PC board.
the destination device: this total effective
• Careful selection and placement of external
impedance should be set to match the trace
components preserve the high frequency
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