THS4601EVM User’s Guide October 2002 High Performance Linear Products SLOU150
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.
EVM IMPORTANT NOTICE Texas Instruments (TI) provides the enclosed product(s) under the following conditions: This evaluation kit being sold by TI is intended for use for ENGINEERING DEVELOPMENT OR EVALUATION PURPOSES ONLY and is not considered by TI to be fit for commercial use.
EVM WARNINGS AND RESTRICTIONS It is important to operate this EVM within the specified input and output ranges described in the EVM User’s Guide.The input supply voltage ( VS) should be 5 V minimum and no greater than 15 V. Differential input signal should be no greater than 4 V. The output current (IO) should be no greater than 100 mA. Exceeding the specified input range may cause unexpected operation and/or irreversible damage to the EVM.
Information About Cautions and Warnings Preface Read This First Information About Cautions and Warnings This book may contain cautions and warnings. This is an example of a caution statement. A caution statement describes a situation that could potentially damage your software or equipment. This is an example of a warning statement. A warning statement describes a situation that could potentially cause harm to you. The information in a caution or a warning is provided for your protection.
Trademarks Electrostatic Sensitive Components This EVM contains components that can potentially be damaged by electrostatic discharge, Always transport and store the EVM in its supplied ESD bag when not in use. Handle using an antistatic wristband. Operate on an anti-static work surface. For more information on proper handling, refer to SSYA008. Related Documentation From Texas Instruments The URL’s below are correct as of the date of publication of this manual.
Contents Contents 1 Introduction and Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.1 Evaluation Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 2 Using the EVM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 3 EVM Applications . . . . . . . . . . . . . . . . . . . .
Contents Figures 1-1 2-1 3-1 3-2 3-3 3-4 3-5 3-6 3-7 3-8 3-9 3-10 3-1 1 3-12 3-13 3-14 3-15 4-1 Schematic of the THS4601EVM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 Test Equipment Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 Default Configuration—DC-Coupled, Dual Power Supply, Non-Inverting Gain Stage . . . 3-1 AC-Coupled, Single Power Supply, Noninverting Gain Stage . . . .
Chapter 1 Introduction and Description This EVM provides a platform for testing the THS4601 in 8-pin SOIC PowerPADt (DDA) package. It contains the high-speed op amp, a number of passive components, and various features and footprints that enable the user to experiment, test, and verify various operational amplifier circuit implementations.
Evaluation Schematic 1.1 Evaluation Schematic As delivered, the EVM has a fully functional example circuit—just add power supplies, a signal source, and monitoring instrument. See Figure 1-1 for a complete schematic diagram.
Evaluation Schematic Figure 1-1. Schematic of the THS4601EVM Z5 100 Ω J1 Z1 0 Ω R3 100 Ω R4 Vin- Z4 * VS+ R1 0 Z6 * R6 R7 * Vin+ Z2 2 * 0Ω 3 7 - TP3 Vout 6 THS4601 J5 GND Z9 R8 1 kΩ R5 * J3 Vout Z3 49.9 Ω U1 + 4 R2 49.9 Ω J4 VS- VS+ * J7 Vref J2 * * VS- TP1 J6 VS+ TP2 FB1 FB2 VS+ VS- + + C3 22 µF C4 0.1 µF C5 1000 pF C1 100 pF C6 22 µF C7 0.
Chapter 2 Using the EVM Figure 2-1 shows how to connect power supplies, signal source and monitoring instrument. It is recommended that the user connect the EVM as shown to avoid damage to the EVM or the op amp installed on the board. Figure 2-1.
Chapter 3 EVM Applications Example applications are presented in this chapter. These applications are meant to demonstrate the most popular circuits to the user, but many other circuits can be constructed. The user is encouraged to experiment with different circuits, exploring new and creative design techniques. That is the function of an evaluation board. 3.1 Noninverting Gain Stages Figure 3-1.
Noninverting Gain Stages Figure 3-2. AC-Coupled, Single Power Supply, Noninverting Gain Stage Z1 R1 0Ω R3 100 Ω Z5 100 Ω VS+ R6 VS+ TP3 Vout Vref J7 J2 Vin+ 7 R7 2 Z2 3 + U1 6 Z3 J3 Vout THS4601 R2 49.9 Ω 4 R5 R8 1 kΩ *Power supply decoupling is not shown Z1 through Z3 are populated with dc-blocking capacitors, selected so they do not interfere with the frequencies that are of interest. These capacitors create high pass characteristics.
Inverting Gain Stages 3.2 Inverting Gain Stages Figure 3-3. DC-Coupled, Dual Power Supply, Inverting Gain Stage J1 Vin- Z1 0 Z5 100 R3 100 R1 61.9 VS+ TP3 Vout 7 2 Z2 0 3 - 6 + THS4601 4 R2 0 J3 Vout Z3 49.
Transimpedance Amplifier prefers, an external potential can be introduced at J7, and use only resistors R7 and R5. If the source of VS+ in the system is noisy, and there is a less noisy potential available in the system, it can be connected to J7. R7 and R5 can then be used as a voltage divider off the reference attached to J7 to create the VS+ divided-by-2 potential. The gain measured from J1 to J3 is 1 in the passband, and is still determined by: V out V in* + * Z5 (in the passband of the stage).
Transimpedance Amplifier signal also places requirements on the amplifier’s dynamic range. Knowledge of the source’s output current levels, coupled with a desired voltage swing on the output, dictates the value of the feedback resistor, R4. The transfer function from input to output is VOUT = IINRF. The large gain-bandwidth product of the THS4601 provides the capability for achieving both high transimpedance gain and wide bandwidth simultaneously.
Transimpedance Amplifier Z5 + 1 ) p(R4)GBP Ǹǒ 1 p(R4)GBP Ǔ 2 ) 4C S p(R4)GBP 2 Once the optimal feedback capacitor has been selected, the transimpedance bandwidth can be calculated: F –3dB + Ǹ GBP ǒ Ǔ 2p(R4) C ) Z5 S The total source capacitance CS is the sum of several distinct capacitances as shown in Figure 3-6. Figure 3-6.
Transimpedance Amplifier Figure 3-7. Transimpedance Circuit Bode Plot Gain AOL -20 dB/ Decade 20 dB/Decade Rate-of-Closure Noise Gain GBP 20 dB/ Decade 0 f Zero Pole The performance of the THS4601 has been measured for a variety of transimpedance gains with a variety of source capacitances. The achievable bandwidths of the various circuit configurations are summarized numerically in the data sheet, SLOS388.
T-Network Gain Stages Figure 3-8. Transimpedance Gains 10 kΩ TRANSIMPEDANCE BANDWIDTH FOR VARIOUS SOURCE CAPACITANCES 100 kΩ TRANSIMPEDANCE BANDWIDTH FOR VARIOUS SOURCE CAPACITANCES 90 105 Transimpedance Gain - dB Transimpedance Gain - dB 100 85 CS = 18 pF, CF = 2.2 pF 80 CS = 47 pF, CF = 3.3 pF 75 CS = 100 pF, CF = 3.9 pF 70 CS = 220 pF, CF = 5.6 pF 65 10 k 100 k CS = 18 pF, CF = 0.6 pF 95 90 CS = 47 pF, CF = 0.6 pF 85 80 CS = 100 pF, CF = 1.5 pF 75 70 CS = 220 pF, CF = 1.
T-Network Gain Stages Figure 3-9. Simplified EVM Schematic for Inverting Gain R4 Z4 Z6 VS+ J1 Vin- 7 2 3 R3 + J3 Vout U1 6 THS4601 4 VS- The following assumes that Z4 and Z6 are resistors. Gain for the T-network stage is defined by the expression: V out V in ǒ + – R4 ) Z4 ) Z4 R3 Z6 R4 R3 Ǔ Looking at the expression above, the gain of the circuit is the standard inverting gain (the first term), modified by the second term.
Transimpedance Networks Figure 3-10. Simplified EVM Schematic for Noninverting Gain Z4 R4 Z6 VS+ 7 2 3 R3 J2 Vin+ J3 Vout U1 6 + THS4601 4 VS- 3.5 Transimpedance Networks The components R4, and Z4 through Z6 can be used to form several transimpedance networks. Transimpedance networks are used to implement custom filter responses based on the location of poles and zeros. Pole / zero filter design is beyond the scope of this EVM manual.
Transimpedance Networks Figure 3-13. Single Real Pole and Single Real Zero (Second Configuration) Z5 Imag Z4 R4 Vin X Real O Iout Figure 3-14. Two Real Poles, One Real Zero Z5 R4 Imag Z4 Vin X O Real X Iout Figure 3-15.
Chapter 4 EVM Hardware Description Table 4-1. THS4601EVM Bill of Materials Item Description SMD Reference Size Desginator PCB Qty. Manfacturer’s Part No. Distributor’s Part No. 1 Bead, ferrite, 3A, 80 Ω 1206 FB1, FB2 2 (Steward) HI1206N800R-00 (Digi-Key) 240-010-1-ND 2 Capacitor, 22 µf, tantalum, 35 V, 10% D C3, C6 2 (AVX) TAJD226K035R (Garrett) TAJD226K035R 3 Open 0805 C9, C10 2 4 Capacitor, 0.
Figure 4-1.
