Datasheet

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THS4520 EVM
49.9 W
−
+
J1
R12
C15
0.22 Fm
R1
53.6 W
R3
487 W
R4
487 W
R2
53.6 W
J2
TP2
C14
0.1 mF
C11
0.1 mF
TP1
U1
11
2
12
4
Vocm
9
TP3
R6
499 W
1315
14 16
PwrPad
10
V
O−
V
O+
3
75
86
VCC
499 W
VCC
R5
PD
C9
0.1 mF
C10
0.1 mF
C4
10 mF 10 mF
C6
VEE
V
S−
J4 J5
GND
VEE
V
S+
J6
C3
10 mF 10 mF
C5
0.1 mF 0.1 mF
C12 C13
J8
J3
T1
16
5
4
R9
open
R7
86.6 W
R8
86.6 W
R10
open
XFMR_ADT1−1WT
3
R11
69.8 W
J7
C8
open
C7
open
C1
open
C2
open
VCC
VEE
6481529
THS4520RGT
THS4520
SLOS503B – SEPTEMBER 2006 – REVISED JULY 2007
Figure 72 is the THS4520 EVAL1 EVM schematic, layers 1 through 4 of the PCB are shown Figure 73 , and
Table 5 is the bill of material for the EVM as supplied from TI.
Figure 72. THS4520 EVAL1 EVM Schematic
Figure 73. THS4520 EVAL1 EVM Layer 1 through 4
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