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DV
OD
ǒ
V
IO
Ǔ
+ V
IO
RG ) RF
RG
+ V
IO
ńb
(5)
b +
RG
RG ) RF
(6)
DV
OD
ǒ
I
IO
Ǔ
+ I
IO
RF
(7)
DV
OD
ǒ
I
IB
, I
IO
Ǔ
+ 2
I
IB
ǒ
R
EQ1
* R
EQ2
Ǔ
) I
IO
ǒ
R
EQ1
) R
EQ2
Ǔ
ǒ
b
1
) b
2
Ǔ
-16
-14
-12
-10
-8
-6
-4
-2
0
2
4
0.1 1 10 100 1000
f-Frequency-MHz
Gain-dB
R =open
C
R =200
NG=7
C
W
R =R =487
NG=4
C G
W
DC ERRORS IN A FULLY DIFFERENTIAL
Summary
DV
OD
ǒ
V
OCM
, V
ICM
Ǔ
+ 2
ǒ
V
OCM
* V
ICM
Ǔ
ǒ
b
1
* b
2
Ǔ
ǒ
b
1
) b
2
Ǔ
DEPENDENCE OF HARMONIC DISTORTION
RF
1
RG
2
V
OUT-
Source
+
-
+
-
+
-
+
-
+
-
-
+
V
I
V /2
ID
V /2
ID
V
IN+
V
IN-
RG
1
V /2
IO
V /2
IO
I
IB+
V
P
V
N
I
IB-
V
S+
V
S+
V
OCM
RF
2
V
OD
V
OUT+
Ideal
FDA
THS4520
SLOS503B – SEPTEMBER 2006 – REVISED JULY 2007
and the reduced bandwidth due to increased noise When there is no mismatch between the feedback
gain when the circuit is configured for low forward networks (RF
1
= RF
2
and RG
1
= RG
2
) the output
gain. Note that using noise gain compensation error due to the input offset voltage is given by:
increases the circuit output noise and decreases the
circuit bandwidth. Compared to the default
configuration (no R
C
) using R
C
= 200 Ω and R
C
=
where β is often called the feedback factor.
487 Ω increases the circuit output noise by
approximately 10.9dB and 6dB respectively.
For additional information, see the applications note
Fully Differential Amplifiers (SLOA054 ).
The output error due to the input offset current is
given by:
If there is mismatch (RF
1
≠ RF
2
or RG
1
≠ RG
2
), then
the output error due to the input bias currents is:
(8)
Where I
IB
= (I
IB+
+ I
IB–
)/2, R
EQ1,2
= RF
1,2
|| RG
1,2
and
Figure 66. THS4520 EVM Small Signal Response
β
1,2
= RG
1,2
/(RG
1,2
+ RF
1,2
).
With and Without Noise Gain Compensation
There is an additional contribution to the output error
if the input and output common-mode voltages are
mismatched:
AMPLIFIER
A DC error model of a fully differential voltage
(9)
feedback amplifier shown in the following circuit
Note that this source of output error will be negligible
diagram. The output error has four contributing
if the two feedback paths are well matched. The
factors in this model:
analysis that leads to the results shown above is
1. Input offset voltage (V
IO
).
beyond the scope of this section. An applications
2. Input offset current (I
IO
).
note that shows the detailed analysis will be
available in the near future.
3. Input bias currents (I
IB+
, I
IB–
) interacting with
mismatched feedback networks.
4. Mismatch between input and output
ON DEVICE OUTPUT SWING AND SIGNAL
common-mode voltages interacting with the
FREQUENCY
mismatched feedback networks.
Typical plots of HD2 or HD3 usually show the
dependence of these parameters upon a single
variable, like frequency, output swing, load, or circuit
gain. Operating conditions of interest are usually
dependent on several variables that are often spread
across several different plots. This forces the
designer to interpolate across several plots in an
attempt to capture the parameters and operating
conditions for his/her application.
Unlike typical plots where HD2 or HD3 is plotted
against a single variable, the plots below show
constant contours of THS4520 HD2 and HD3 plotted
against the joint parameters of device output swing
and signal frequency. These two parameters are of
24
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