Datasheet

-0.4
-0.2
0
0.2
0.4
0.6
0.8
0 5 10 15 20
t-Time- sm
V
oltage-V
CM
V
Signal
V
S-
R
F
R
F
R
G
R
G
R
IT
R
IT
R
PD
R
PD
R
O
R
O
V
OUT+
V
OUT-
THS4508
R
C
C
S
R
S
V =3.75Vto5V
S+
Video Buffer
-1
-0.5
0
0.5
1
1.5
0 5 10 15 20
t-Time- sm
V
OD
-VideoBufferOutput- V
THS4508 + ADS5500 Combined Performance
THS4508
V
IN
R =75
S
W
V
Signal
V
S-
V
CM
R
O
R
O
V
OD
V =5V
S+
175 W
175 W
Video
Source
75 W
130 W
130 W
348 W
348 W
THS4508
www.ti.com .................................................................................................................................... SLAS459E – SEPTEMBER 2005 – REVISED SEPTEMBER 2008
Table 4. R
PD
Values for Various Gains,
V
S+
= 3.75 V, AC-Coupled Signal Source
Gain R
F
R
G
R
IT
R
PD
6 dB 348 Ω 169 Ω 64.9 Ω 80.6 Ω
10 dB 348 Ω 102 Ω 78.7 Ω 90.9 Ω
14 dB 348 Ω 61.9 Ω 115 Ω 90.9 Ω
20 dB 348 Ω 40.2 Ω 221 Ω 77.6 Ω
Figure 55. Y' Signal With 3-Level Sync and Video
Signal
Figure 53. THS4508 AC-Coupled Single-Source
Supply Range From 3.75 V to 5 V With R
PD
Used
To Set V
IC
Figure 54 shows a possible application of the
THS4508 as a dc-coupled video buffer with a gain of
2. Figure 55 shows a plot of the Y' signal originating
from a HDTV 720p video system. The input signal
includes a 3-level sync (minimum level at – 0.3 V),
and the portion of the video signal with maximum
amplitude of 0.7 V. Although the buffer draws its
Figure 56. Video Buffer Differential Output Signal
power from a 5-V single-ended power supply, internal
level shifters allow the buffer to support input signals
which are as much as – 0.3 V below ground. This
allows maximum design flexibility while maintaining a
The THS4508 is designed to be a high-performance
minimum parts count. Figure 56 shows the differential
drive amplifier for high-performance data converters
output of the buffer. Note that the dc-coupled
such as the ADS5500 14-bit 125-MSPS ADC.
amplifier can introduce a dc offset on a signal applied
Figure 57 shows a circuit combining the two devices,
at its input
and Figure 58 shows the combined SNR and SFDR
performance versus frequency with – 1 dBFS input
signal level sampling at 125 MSPS. The THS4508
amplifier circuit provides 10 dB of gain, and converts
the single-ended input signal to a differential output
signal. The default common-mode output of the
THS4508 (2.5 V) is not compatible with the required
common-mode input of the ADS5500 (1.55 V), so
dc-blocking capacitors are added (0.22 µ F). Note that
a biasing circuit (not shown in Figure 57 ) is needed to
provide the required common-mode, dc-input for the
ADS5500. The 100- Ω resistors and 2.7-pF capacitor
between the THS4508 outputs and ADS5500 inputs
along with the input capacitance of the ADS5500 limit
Figure 54. Single-Supply Video Buffer, Gain = 2
the bandwidth of the signal to 115 MHz ( – 3 dB). For
testing, a signal generator is used for the signal
source. The generator is an ac-coupled 50- Ω source.
A band-pass filter is inserted in series with the input
to reduce harmonics and noise from the signal
Copyright © 2005 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 21
Product Folder Link(s): THS4508