Datasheet

2
1.5
1
0
−40 −20 0 20
− Maximum Power Dissipation − W
2.5
3
3.5
40 60 80
T
A
− Ambient Temperature − °C
P
D
8-Pin DGN Package
θ
JA
= 170°C/W for 8-Pin SOIC (D)
θ
JA
= 58.4°C/W for 8-Pin MSOP (DGN)
Τ
J
= 150°C, No Airflow
0.5
8-Pin D Package
P =
Dmax
T T-
MAX A
q
JA
THS4500
THS4501
www.ti.com SLOS350F –APRIL 2002–REVISED OCTOBER 2011
6. The top-side solder mask should leave the Maximum power dissipation levels are depicted in
terminals of the package and the thermal pad Figure 114 for the two packages. The data for the
area with its five holes exposed. The bottom-side DGN package assumes a board layout that follows
solder mask should cover the five holes of the the PowerPAD layout guidelines referenced above
thermal pad area. This configuration prevents and detailed in the PowerPAD application notes in
solder from being pulled away from the thermal the Additional Reference Material section at the end
pad area during the reflow process. of the data sheet.
7. Apply solder paste to the exposed thermal pad
area and all of the IC terminals.
8. With these preparatory steps in place, the IC is
simply placed in position and run through the
solder reflow operation as any standard
surface-mount component. This process results
in a part that is properly installed.
POWER DISSIPATION AND THERMAL
CONSIDERATIONS
The THS4500 family of devices does not incorporate
automatic thermal shutoff protection, so the designer
must take care to ensure that the design does not
violate the absolute maximum junction temperature of
the device. Failure may result if the absolute
maximum junction temperature of +150°C is
exceeded. For best performance, design for a
maximum junction temperature of +125°C. Between
Figure 114. Maximum Power Dissipation vs
+125°C and +150°C, damage does not occur, but the
Ambient Temperature
performance of the amplifier begins to degrade.
When determining whether or not the device satisfies
The thermal characteristics of the device are dictated
the maximum power dissipation requirement, it is
by the package and the PCB. Maximum power
important to not only consider quiescent power
dissipation for a given package can be calculated
dissipation, but also dynamic power dissipation. Often
using the following formula.
times, this consideration is difficult to quantify
because the signal pattern is inconsistent; an
estimate of the RMS power dissipation can provide
visibility into a possible problem.
Where:
P
Dmax
is the maximum power dissipation in the
DRIVING CAPACITIVE LOADS
amplifier (W).
High-speed amplifiers are typically not well-suited for
T
MAX
is the absolute maximum junction
driving large capacitive loads. If necessary, however,
temperature (°C).
the load capacitance should be isolated by two
T
A
is the ambient temperature (°C).
isolation resistors in series with the output. The
θ
JA
= θ
JC
+ θ
CA
requisite isolation resistor size depends on the value
of the capacitance, but 10 Ω to 25 Ω is a good place
θ
JC
is the thermal coefficient from the silicon
to begin the optimization process. Larger isolation
junctions to the case (°C/W).
resistors decrease the amount of peaking in the
θ
CA
is the thermal coefficient from the case to
frequency response induced by the capacitive load,
ambient air (°C/W). (28)
but this decreased peaking comes at the expense ofa
For systems where heat dissipation is more critical,
larger voltage drop across the resistors, increasing
the THS4500 family of devices is offered in an
the output swing requirements of the system.
MSOP-8 package with PowerPAD. The thermal
coefficient for the MSOP PowerPAD package is
substantially improved over the traditional SOIC.
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