Datasheet

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+5V
A
IN+
A
IN−
ADS 5500
R
F
R
G
49 .9
V
IN
From
50 
source
100
1:1
R
F
R
G
CM
CM
0.1
THS4304
THS4304
1k
+3.3 VA +3.3 VD
D
A
0.1
+5V
10 k
V
REF
(= 2.5V)
V
REF
V
REF
V
REF
1nF
1nF
+5V
CM



10 k 
100 
1k
F
F
75
80
85
90
10 20 30 40 50
dB
f − Frequency − MHz
Combined THS4304 and
ADS5500 SFDR
G = 10 dB,
−1 dBFS,
R
F
= 249 Ω,
R
G
= 115 Ω,
SNR = 69.6,
F
S =
125 MSPS
THS4304
SLOS436A – MARCH 2004 – REVISED JULY 2004
The differential topology employed in this circuit provides for significant suppression of the 2nd-order harmonic
distortion of the amplifiers. This, along with the superior 3rd-order harmonic distortion performance of the
amplifiers, results in the SFDR performance of the circuit (at frequencies up to 40 MHz) being set by higher-order
harmonics generated by the sampling process of the ADS5500.
The amplifier circuit (with resistor divider for bias voltage generation) requires a total of 185 mW of power from a
single 5-V power supply.
Figure 55. Differential ADC Drive Amplifier Circuit
Figure 56. SFDR Performance versus Frequency – THS4304 Driving ADS5500
22