Datasheet

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2
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4 5
8
7
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1
2
3
5
4
V
OUT
V
S
−
IN+
V
S
+
IN−
IN+
IN−
NC
V
S
−
NC
V
S
+
V
OUT
TOP VIEW TOP VIEWDBV D and DGK
NOTE: NC indicates there is no internal connection to these pins.
V
OUT
DISSIPATION RATINGS
THS4304
SLOS436A – MARCH 2004 – REVISED JULY 2004
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
PINOUT DRAWING
PACKAGING / ORDERING INFORMATION
TRANSPORT MEDIA,
PACKAGED DEVICES PACKAGE TYPE PACKAGE MARKINGS
QUANTITY
THS4304DBVT Tape and Reel, 250
SOT-23-5 AKW
THS4304DBVR Tape and Reel, 3000
THS4304D Rails, 75
SOIC-8 —
THS4304DR Tape and Reel, 2500
THS4304DGK Rails, 100
MSOP-8 AKU
THS4304DGKR Tape and Reel, 2500
POWER RATING
(2)
θ
JC
θ
JA
PACKAGE
(°C/W) (°C/W)
(1)
T
A
≤ 25°C T
A
= 85°C
DBV (5) 55 255.4 391 mW 156 mW
D (8) 38.3 97.5 1.02 W 410 mW
DGK (8) 71.5 180.8 553 mW 221 mW
(1) This data was taken using the JEDEC standard High-K test PCB.
(2) Power rating determined with a junction temperature of 125°C. This is the point where distortion starts to substantially increase. Thermal
management of the final PCB should strive to keep the junction temperature at or below 125°C for best performance and long-term
reliability.
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