Datasheet

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R4
49.9 Ω
_
+
R
f
V
I
R
g
8
7
6
5
R2
49.9 Ω
R3
*
J2
V
O
U1
1 2 3 4
+
22 µF
NC
C3
FB1
*
C7
47 pF
C8
C5
0.1 µF
R4
30.1 Ω
11 10 912
J4
V
S−
+
22 µF
*
C6
47 pF
C9
C4
0.1 µF
R5
30.1 Ω
FB2
V
S+
J3
14
13
16
PD
1 µF
C1
J1
J6
* = Not populated
C2
6454762
A
THS4303
SLOS421B – NOVEMBER 2003 – REVISED JANUARY 2005
Figure 51. Typical THS4303 EVM Circuit Configuration Figure 52. THS4303EVM Layout
(Top Layer and Silkscreen Layer)
Figure 53. THS4303EVM Board Layout Figure 54. THS4303EVM Board Layout
(Ground Layers 2 and 3) (Bottom Layer)
21