Datasheet
www.ti.com
ABSOLUTE MAXIMUM RATINGS
(TOP VIEW)
RGT PACKAGE
1
2
3
4
5
6 7 8
12
11
10
9
16 15 14 13
NC = No connect
V
S−
V
S
+
V
OUT
V
IN+
NC
PD
V
IN−
R
g
R
f
THS4303
SLOS421B – NOVEMBER 2003 – REVISED JANUARY 2005
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated
circuits be handled with appropriate precautions. Failure to observe proper handling and installation
procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision
integrated circuits may be more susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
over operating free-air temperature range unless otherwise noted
(1)
UNIT
V
S
Supply voltage 6 V
V
I
Input voltage ± V
S
I
O
Output current 200 mA
Continuous power dissipation See Dissipation Rating Table
T
J
(
(2)
)
Maximum junction temperature 150 ° C
T
J
(
(3)
)
Maximum junction temperature, continuous operation, longterm reliability 125 ° C
T
A
Operating free-air temperature range –40 ° C to 85 ° C
T
stg
Storage temperature range –65 ° C to 150 ° C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 300 ° C
ESD ratings:
HBM 3000
CDM 1500
MM 200
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
(2) The THS4303 device may incorporate a PowerPAD™ on the underside of the chip. This acts as a heatsink and must be connected to a
thermally dissipative plane for proper power dissipation. Failure to do so may result in exceeding the maximum junction temperature
which can permanently damage the device. See TI technical brief SLMA002 and SLMA004 for more information about utilizing the
PowerPAD thermally enhanced package.
(3) The absolute maximum temperature under any condition is limited by the constraints of the silicon process.
2