Datasheet

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PowerPAD™ DESIGN CONSIDERATIONS
THS4303
SLOS421B – NOVEMBER 2003 – REVISED JANUARY 2005
and may be shared among several devices in the destination device: this total effective impedance
same area of the PC board. A very low induct- should be set to match the trace impedance. If
ance path should be used to connect the in- the 6 dB attenuation of a doubly terminated
verting pin of the amplifier to ground. A minimum transmission line is unacceptable, a long trace
of 5 vias as close to the part as possible is can be series-terminated at the source end only.
recommended. Treat the trace as a capacitive load in this case
and set the series resistor value as shown in the
3. Careful selection and placement of external
plot of R
ISO
vs Capacitive Load. This does not
components preserves the high frequency
preserve signal integrity as well as a
performance of the THS4303. Resistors should
doubly-terminated line. If the input impedance of
be a very low reactance type. Surface-mount
the destination device is low, there is some signal
resistors work best and allow a tighter overall
attenuation due to the voltage divider formed by
layout. Axially-leaded parts do not provide good
the series output into the terminating impedance.
high frequency performance, since they have ~
A 50- Ω environment is normally not necessary on
0.8 nH of inductance for every mm of current
board as long as the lead lengths are short, and
path length. Again, keep PC board trace length
in fact, a higher impedance environment im-
as short as possible. Never use wirewound type
proves distortion as shown in the distortion ver-
resistors in a high frequency application. Since
sus load plots. Uncontrolled impedance traces
the output pin and inverting input pin are the most
without double termination results in reflections at
sensitive to parasitic capacitance, always position
each end, and hence, produces PCB resonances.
the terminating resistors, if any, as close as
It is recommended that if this approach is used,
possible to the noninverting and output pins.
the trace length be kept short enough to avoid
Even with a low parasitic capacitance shunting
resonances in the band of interest. For guidance
the external resistors, excessively high resistor
on useful lengths, use equation (1) given in the
values can create significant time constants that
Power Supply Decoupling Techniques section for
can degrade performance. Good axial metal-film
approximate resonance frequencies verses trace
or surface-mount resistors have approximately
length. This relation provides an upper bound on
0.2 pF in shunt with the resistor.
the resonant frequency, because additional ca-
4. Connections to other wideband devices on
pacitive coupling to the trace from other leads or
the board may be made with short direct
the ground plane causes extra distributed loading
traces or through onboard transmission lines.
and slows the signal propagation along the trace.
For short connections, consider the trace and the
5. Socketing a high-speed part like the THS4303
input to the next device as a lumped capacitive
is not recommended. The additional lead length
load. Relatively wide traces (50 mils to 100 mils)
inductance and pin-to-pin capacitance introduced
should be used, preferably with ground and
by the socket creates an extremely troublesome
power planes opened up around them. Estimate
parasitic network, which can make it almost
the total capacitive load and set R
ISO
from the
impossible to achieve a smooth, stable frequency
plot of recommended R
ISO
vs Capacitive Load.
response. Best results are obtained by soldering
Low parasitic capacitive loads (<4 pF) may not
the THS4303 onto the board.
need an R
ISO
since the THS4303 is nominally
compensated to operate with a 2 pF parasitic
load. Higher parasitic capacitive loads without an
R
ISO
are allowed as the signal gain increases
The THS4303 is available in a thermally-enhanced
(increasing the unloaded phase margin). If a long
PowerPAD family of packages. These packages are
trace is required, and the 6 dB signal loss
constructed using a downset leadframe upon which
intrinsic to a doubly-terminated transmission line
the die is mounted [see Figure 48 (a) and Fig-
is acceptable, implement a matched impedance
ure 48 (b)]. This arrangement results in the lead frame
transmission line using microstrip or stripline
being exposed as a thermal pad on the underside of
techniques (consult an ECL design handbook for
the package [see Figure 48 (c)]. Because this thermal
microstrip and stripline layout techniques). With a
pad has direct thermal contact with the die, excellent
characteristic board trace impedance defined
thermal performance can be achieved by providing a
based on board material and trace dimensions, a
good thermal path away from the thermal pad.
matching series resistor into the trace from the
output of the THS4303 is used as well as a
The PowerPAD package allows both assembly and
terminating shunt resistor at the input of the
thermal management in one manufacturing operation.
destination device. Remember also that the ter-
minating impedance is the parallel combination of
the shunt resistor and the input impedance of the
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