Datasheet

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ADC
R
ISO
IN
IN
CM
_
+
THS4303
R
f
49.9 Ω
V
I
+
22 µF 47 pF 0.1 µF
V
S+
50 Ω Source
R
g
30.1 Ω
FB
FB = Ferrite Bead
*2.5 V
*2.5 V
* = Low Impedance
C
C
C
R
10
12
14
16
18
20
22
1 M 10 M 100 M 1 G
f − Frequency − Hz
Signal Gain − dB
R
L
= 100 Ω
V
S
= 5 V
R
ISO
= 25 Ω, C
L
= 10 pF
R
ISO
= 15 Ω, C
L
= 47 pF
R
ISO
= 10 Ω, C
L
= 100 pF
+
−
R
ISO
C
L
POWER SUPPLY DECOUPLING TECHNIQUES
DRIVING CAPACITIVE LOADS
THS4303
SLOS421B – NOVEMBER 2003 – REVISED JANUARY 2005
The second circuit depicts single-ended ADC drive. sponse flatness, pulse response fidelity, or distortion,
While not recommended for optimum performance the simplest and most effective solution is to isolate
using converters with differential inputs, satisfactory the capacitive load from the feedback loop by in-
performance can sometimes be achieved with single- serting a series isolation resistor between the ampli-
ended input drive. An example circuit is shown here fier output and the capacitive load.
for reference.
The Typical Characteristics show the recommended
isolation resistor vs capacitive load and the resulting
frequency response at the load. Parasitic capacitive
loads greater than 2 pF can begin to degrade the
performance of the THS4303. Long PC board traces,
unmatched cables, and connections to multiple de-
vices can easily cause this value to be exceeded.
Always consider this effect carefully, and add the
recommended series resistor as close as possible to
the THS4303 output pin (see Board Layout
Guidelines).
The criterion for setting this R
(ISO)
resistor is a
maximum bandwidth, flat frequency response at the
load.
Figure 46. Driving an ADC With a Single-Ended
Input
NOTE:
Figure 47. Driving Capacitive Loads
For best performance,
high-speed ADCs should
be driven differentially.
AND RECOMMENDATIONS
See the THS4500 family
of devices for more infor-
Power supply decoupling is a critical aspect of any
mation.
high-performance amplifier design process. Careful
decoupling provides higher quality ac performance
(most notably improved distortion performance). The
following guidelines ensure the highest level of per-
One of the most demanding, and yet very common,
formance.
load conditions for an op amp is capacitive loading.
Often, the capacitive load is the input of an A/D
1. Place decoupling capacitors as close to the
converter, including additional external capacitance,
power supply inputs as possible, with the goal of
which may be recommended to improve A/D linearity.
minimizing the inductance of the path from
High-speed amplifiers like the THS4303 can be very
ground to the power supply. Inductance in series
susceptible to decreased stability and closed-loop
with the bypass capacitors will degrade perform-
response peaking when a capacitive load is placed
ance. Note that a narrow lead or trace has about
directly on the output pin. When the amplifier's
0.8 nH of inductance for every millimeter of
open-loop output resistance is considered, this ca-
length. Each printed-circuit board (PCB) via also
pacitive load introduces an additional pole in the
has between 0.3 and 0.8 nH depending on length
signal path that can decrease the phase margin.
and diameter. For these reasons, it is rec-
When the primary considerations are frequency re-
ommended to use a power supply trace about the
width of the package for each power supply lead
16