Datasheet

L(nH) + Kȏ
ƪ
ln
2ȏ
W ) T
) 0.223
W ) T
ȏ
) 0.5
ƫ
where:
W = Width of trace in inches.
= Length of the trace in inches.
T = Thickness of the trace in inches.
K = 5.08 for dimensions in inches, and K = 2 for dimensions
in cm.
ȏ
R1
R5
J2
Vin+
R6
Vs+
U1
2
3
6
7
4 1
8
J8
Power Down Ref
Vs+
R8
C8
Vs −
R4
R7
C7
J9
Power Down
R2
J4
Vout
Vs −
R9
R3
J1
Vin
−
TP1
+
C1
VS−
J7
C6C5
C2
VS+
J5
+
FB2
C4C3
FB1
VS−
GND
VS+
J6
_
+
THS4271
THS4275
SLOS397F –JULY 2002–REVISED OCTOBER 2009 www.ti.com
The peaking in the frequency response is due to the
lead inductance in the feedback path. Each pad and
trace on a PCB has an inductance associated with it,
which in conjunction with the inductance associated
with the package may cause peaking in the frequency
response, causing the device to become unstable.
In order to achieve the maximum performance of the
device, PCB layout is very critical. Texas Instruments
has developed an EVM for the evaluation of the
THS4271 in a gain of 1. The EVM is shown in
Figure 101 through Figure 104. This EVM is designed
to minimize peaking in the unity gain configuration.
Minimizing the inductance in the feedback path is
critical for reducing the peaking of the frequency
response in unity gain. The recommended maximum
inductance allowed in the feedback path is 4 nH. This
can be calculated by using Equation 8.
(8)
space
space
space
Figure 95. THS4271/THS4275 EVM
Circuit Configuration
32 Submit Documentation Feedback Copyright © 2002–2009, Texas Instruments Incorporated
Product Folder Link(s): THS4271 THS4275