Datasheet

_
+
R
f
4kT = 1.6E-20J
at 290K
THS4271/THS4275
I
BN
E
O
E
RF
R
S
E
RS
I
BI
R
g
E
NI
4kTR
S
4kT
R
g
4kTR
f
E
O
+
ǒ
E
2
NI
)
ǒ
I
BN
R
S
Ǔ
2
) 4kTR
S
Ǔ
NG
2
)
ǒ
I
BI
R
f
Ǔ
2
) 4kTR
f
NG
Ǹ
E
O
+ E
2
NI
)
ǒ
I
BN
R
S
Ǔ
2
) 4kTR
S
)
ǒ
I
BI
R
f
NG
Ǔ
2
)
4kTR
f
NG
Ǹ
-3
-2.5
-2
-1.5
-1
-0.5
0
0.5
1 M 10 M
100 M
f - Frequency - Hz
Normalized Gain - dB
FREQUENCY RESPONSE
vs
CAPACITIVE LOAD
R
L
= 499 Ω
V
S
=±5 V
R
(ISO)
= 25 Ω C
L
= 10 pF
R
(ISO)
= 15 Ω C
L
= 100 pF
R
(ISO)
= 10 Ω C
L
= 50 pF
THS4271
THS4275
www.ti.com SLOS397F –JULY 2002–REVISED OCTOBER 2009
additional pole in the signal path that can decrease
the phase margin. When the primary considerations
are frequency response flatness, pulse response
fidelity, or distortion, the simplest and most effective
solution is to isolate the capacitive load from the
feedback loop by inserting a series isolation resistor
between the amplifier output and the capacitive load.
This does not eliminate the pole from the loop
response, but rather shifts it and adds a zero at a
higher frequency. The additional zero acts to cancel
the phase lag from the capacitive load pole, thus
increasing the phase margin and improving stability.
The Typical Characteristics show the recommended
isolation resistor vs capacitive load and the resulting
Figure 87. Noise Analysis Model
frequency response at the load. Parasitic capacitive
loads greater than 2 pF can begin to degrade the
The total output spot noise voltage can be computed
performance of the THS4271. Long PCB traces,
as the square of all square output noise voltage
unmatched cables, and connections to multiple
contributors. Equation 4 shows the general form for
devices can easily cause this value to be exceeded.
the output noise voltage using the terms shown in
Always consider this effect carefully, and add the
Figure 87:
recommended series resistor as close as possible to
the THS4271 output pin (see the Board Layout
Guidelines section).
(4)
The criterion for setting this R
(ISO)
resistor is a
maximum bandwidth, flat frequency response at the
Dividing this expression by the noise gain [NG=(1+
load. For a gain of +2, the frequency response at the
R
f
/R
g
)] gives the equivalent input-referred spot noise
output pin is already slightly peaked without the
voltage at the noninverting input, as shown in
capacitive load, requiring relatively high values of
Equation 5:
R
(ISO)
to flatten the response at the load. Increasing
the noise gain also reduces the peaking.
(5)
Evaluation of these two equations for the circuit and
component values shown in Figure 75 will give a total
output spot noise voltage of 12.2 nV/√Hz and a total
equivalent input spot noise voltage of 6.2 nV/√Hz.
This includes the noise added by the resistors. This
total input-referred spot noise voltage is not much
higher than the 3-nV/√Hz specification for the
amplifier voltage noise alone.
Driving Capacitive Loads
One of the most demanding, and yet very common,
load conditions for an op amp is capacitive loading.
Often, the capacitive load is the input of an A/D
converter, including additional external capacitance,
which may be recommended to improve A/D linearity.
Figure 88. Isolation Resistor Diagram
A high-speed, high open-loop gain amplifier like the
THS4271 can be very susceptible to decreased
stability and closed-loop response peaking when a
capacitive load is placed directly on the output pin.
When the amplifier open-loop output resistance is
considered, this capacitive load introduces an
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